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preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s pmc-sierra, inc. 105 - 8555 baxter place burnaby, bc canada v5a 4v7 604 .415.6000 pm5381 s / uni- 2488 s/uni-2488 saturn user network interface for 2488 mbit/s datasheet proprietary and confidential preliminary issue 1: march 2000
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use i contents 1 features ...................................................................................................................... ......................1 1.1 g eneral ............................................................................................................................... ...........1 1.2 sonet s ection and l ine / sdh r egenerator and m ultiplexer s ection ...................................2 1.3 sonet p ath / sdh h igh o rder p ath ...........................................................................................3 1.4 t he r eceive atm p rocessor ........................................................................................................3 1.5 t he r eceive pos p rocessor ........................................................................................................4 1.6 t he t ransmit atm p rocessor ......................................................................................................4 1.7 t he t ransmit pos p rocessor ......................................................................................................4 2 applications.................................................................................................................. ...................6 3 references.................................................................................................................... ...................7 4 definitions................................................................................................................... ......................9 5 application examples .......................................................................................................... ......10 6 block diagram ................................................................................................................. .............13 7 description................................................................................................................... ..................17 8 pin diagrams.................................................................................................................. .................19 9 sdpin description............................................................................................................. ............20 9.1 s erial l ine s ide i nterface s ignals (7) .......................................................................................20 9.2 c locks and a larms (7).................................................................................................................21 9.3 r eceive s ection /l ine /p ath o verhead e xtraction s ignals (6) .................................................23 9.4 t ransmit s ection /l ine /p ath o verhead i nsertion s ignals (7)...................................................24 9.5 s ystem s ide u topia and pos s ignals (84) .................................................................................28 9.6 aps s erial d ata i nterface (20) ..................................................................................................37 9.7 m icroprocessor i nterface s ignals (37) ...................................................................................39 9.8 jtag t est a ccess p ort (tap) s ignals (5) .................................................................................40 9.9 a nalog m iscellaneous s ignals (10)...........................................................................................41 9.10 a nalog p ower and g round (107) ...............................................................................................42 9.11 d igital p ower and g round ..........................................................................................................44 10 functional description....................................................................................................... ..50 10.1 r eceive l ine i nterface ................................................................................................................50 10.2 sonet/sdh r eceive l ine i nterface (srli)...............................................................................51 10.3 r eceive r egenerator and m ultiplexor p rocessor (rrmp) ...................................................51 10.4 r eceive t ail t race p rocessor (rttp) ......................................................................................53 10.5 r eceive h igh o rder p ath p rocessor (rhpp)...........................................................................54 10.6 sonet/sdh v irtual c ontainer a ligner (svca) ......................................................................62
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use ii 10.7 r eceive c ell and f rame p rocessor (rcfp)..............................................................................65 10.8 r eceive s calable d ata q ueue (rxsdq).....................................................................................70 10.9 r eceive p hy i nterface (rxphy) .................................................................................................71 10.10 t ransmit l ine i nterface ..........................................................................................................71 10.11 sonet/sdh t ransmit l ine i nterface (stli)..........................................................................72 10.12 t ransmit r egenerator m ultiplexor p rocessor (trmp) .....................................................72 10.13 t ransmit t ail t race p rocessor (tttp) .................................................................................75 10.14 t ransmit h igh o rder p ath p rocessor (thpp)......................................................................76 10.15 t ransmit c ell and f rame p rocessor (tcfp) ........................................................................76 10.16 t ransmit s calable d ata q ueue (txsdq) ...............................................................................79 10.17 t ransmit p hy i nterfaces (rxphy and txphy) .....................................................................79 10.18 sonet/sdh b it e rror r ate m onitor (sber) .......................................................................80 10.19 sonet/sdh a larm r eporting c ontroller (sarc) .............................................................80 10.20 sonet/sdh i nband e rror r eport p rocessor (sirp).........................................................81 10.21 aps s erial d ata i nterface ......................................................................................................82 10.22 jtag t est a ccess p ort i nterface .........................................................................................83 10.23 m icroprocessor i nterface .....................................................................................................83 11 normal mode register description .................................................................................97 12 operation.................................................................................................................... ...............430 12.2 sonet/sdh f rame m appings and o verhead b yte u sage ......................................................433 12.3 pos/hdlc d ata s tructure ......................................................................................................438 12.4 s etting at m m ode of o peration ..............................................................................................439 12.5 s etting p acket o ver sonet/sdh m ode of o peration .........................................................439 12.6 b it e rror r ate m onitor ............................................................................................................439 12.7 c locking o perations ................................................................................................................439 12.8 l oopback o peration ..................................................................................................................439 12.9 b oard d esign r ecommendations ..............................................................................................440 12.10 p ower s upplies ......................................................................................................................440 12.11 i nterfacing to ecl or pecl d evices ...................................................................................440 13 functional timing............................................................................................................ .......441 13.1 s erial l ine i nterface .................................................................................................................441 13.2 atm u topia l evel 3 s ystem i nterface .....................................................................................441 13.3 p acket o ver sonet/sdh (pos) l evel 3 s ystem i nterface ..................................................443 13.4 s ection and l ine d ata c ommunication c hannels .....................................................................446 13.5 s/uni-2488 c onceptual r egions .............................................................................................446 14 test features description.................................................................................................447 15 functional timing............................................................................................................ .......448 16 absolute maximum ratings ................................................................................................449 17 d.c. characteristics ......................................................................................................... ....450
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use iii 18 microprocessor interface timing characteristics..............................................453 19 a.c. timing characteristics ...............................................................................................457 19.1 aps p ort i nterface ..................................................................................................................461 20 ordering and thermal information...............................................................................463 21 mechanical information .....................................................................................................46 4
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use iv list of registers register 0000h: s/uni-2488 identity, and global performance monitor update ......98 register 0001h: s/uni-2488 master reset, configuration, and loopback....................99 register 0003h: s/uni-2488 clock monitors ............................................................................102 register 0004h: s/uni-2488 master interrupt status #1 ....................................................104 register 0005h: s/uni-2488 master interrupt status #2 ....................................................105 register 0006h: s/uni-2488 master interrupt status #3 ....................................................106 register 0007h: s/uni-2488 master interrupt status #4 ....................................................107 register 0008h: s/uni-2488 master interrupt status #5 ....................................................108 register 0009h: s/uni-2488 master interrupt status #6 ....................................................110 register 000ah: s/uni-2488 master interrupt status #7....................................................112 register 000bh: unused......................................................................................................... ..........113 register 000ch: aps input telecombus synchronization delay ...................................114 register 000dh: aps output telecombus synchronization delay ...............................115 register 000eh: s/uni-2488 diagnostics....................................................................................116 register 000fh: s/uni-2488 free register .................................................................................118 register 0010h: rx2488 analog interrupt control/status .............................................119 register 0011h: rx2488 analog cru control .........................................................................122 register 0012h: rx2488 analog cru clock training configuration and status ....125 register 0013h: rx2488 analog prbs control.......................................................................127 register 0014h: rx2488 analog pattern register................................................................129 register 0030h: srli clock configuration .............................................................................130 register 0031h: srli pgm clock configuration....................................................................132
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use v register 0038h: stli clock configuration .............................................................................134 register 0039h: stli pgm clock configuration ....................................................................135 the programmable transmit clock frequency selection (pgmtclksel) bit selects the frequency of the pgmtclk output clock. when pgmtclksel is set high, pgmtclk is a nominal 8 khz clock. when pgmtclksel is set to logic zero, pgmtclk is a nominal register 0040h: rrmp configuration ............................................136 register 0041h: rrmp status.................................................................................................... .....138 register 0042h: rrmp interrupt enable ..................................................................................140 register 0043h: rrmp interrupt status ...................................................................................141 register 0044h: rrmp receive aps............................................................................................... 143 register 0045h: rrmp receive ssm ..............................................................................................1 44 register 0046h: rrmp ais enable ................................................................................................ .145 register 0047h: rrmp section bip error counter...............................................................147 register 0048h: rrmp line bip error counter (lsb) ............................................................148 register 0049h: rrmp line bip error counter (msb) ...........................................................148 register 004ah: rrmp line rei error counter (lsb) ...........................................................149 register 004bh: rrmp line rei error counter (msb) ..........................................................149 register 0080h: trmp configuration.........................................................................................150 register 0081h: trmp register insertion ................................................................................153 register 0082h: trmp error insertion .....................................................................................156 register 0083h: trmp transmit j0 and z0 .................................................................................158 register 0084h: trmp transmit e1 and f1 .................................................................................159 register 0085h: trmp transmit d1d3 and d4d12 .....................................................................160 register 0086h: trmp transmit k1 and k2 ................................................................................161 register 0087h: trmp transmit s1 and z1 .................................................................................162
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use vi register 0088h: trmp transmit z2 and e2 .................................................................................163 register 0089h: trmp transmit h1 and h2 mask.....................................................................164 register 008a: trmp transmit b1 and b2 mask.......................................................................165 register 00a0h: trmp aux2 configuration..............................................................................166 register 00c0h: trmp aux3 configuration..............................................................................166 register 00e0h: trmp aux4 configuration ..............................................................................166 register 00a2h: trmp aux2 error insertion ..........................................................................167 register 00c2h: trmp aux3 error insertion ..........................................................................167 register 00e2h: trmp aux4 error insertion ..........................................................................167 register 0110h: sber configuration .........................................................................................168 register 0111h: sber status.................................................................................................... ......170 register 0112h: sber interrupt enable ...................................................................................171 register 0113h: sber interrupt status....................................................................................172 register 0114h: sber sf berm accumulation period (lsb) ...............................................173 register 0115h: sber sf berm accumulation period (msb)...............................................173 register 0116h: sber sf berm saturation threshold (lsb).............................................174 register 0117h: sber sf berm saturation threshold (msb) ............................................174 register 0118h: sber sf berm declaring threshold (lsb) ..............................................175 register 0119h: sber sf berm declaring threshold (msb)..............................................175 register 011ah: sber sf berm clearing threshold (lsb) ................................................176 register 011bh: sber sf berm clearing threshold (msb)................................................176 register 011ch: sber sd berm accumulation period (lsb) ..............................................177 register 011dh: sber sd berm accumulation period (msb)..............................................177 register 011eh: sber sd berm saturation threshold (lsb) ............................................178
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use vii register 011fh: sber sd berm saturation threshold (msb) ...........................................178 register 0120h: sber sd berm declaration threshold (lsb) .........................................179 register 0121h: sber sd berm declaration threshold (msb) ........................................179 register 0122h: sber sd berm clearing threshold (lsb) ................................................180 register 0123h: sber sd berm clearing threshold (msb)................................................180 register 0130h: rttp section indirect address ...................................................................181 register 0131h: rttp section indirect data ...........................................................................183 register 0132h: rttp section trace unstable status .......................................................184 register 0133h: rttp section trace unstable interrupt enable ................................185 register 0134h: rttp section trace unstable interrupt status .................................186 register 0135h: rttp section trace mismatch status .......................................................187 register 0136h: rttp section trace mismatch interrupt enable.................................188 register 0137h: rttp section trace mismatch interrupt status .................................189 indirect register 00h: rttp section trace configuration .............................................190 indirect register 40h to 7fh: rttp section captured trace .........................................192 indirect register 80h to bfh: rttp section accepted trace .........................................193 indirect register c0h to ffh: rttp section expected trace .........................................194 register 0138h: tttp section indirect address....................................................................195 register 0139h: tttp section indirect data............................................................................197 indirect register 0138h: tttp section trace configuration .........................................198 indirect register 40h to 7fh: tttp section trace ...............................................................199 register 0200h: rhpp sts-1/stm-0 #1 through #12 indirect address register 0280h: rhpp sts-1/stm-0 #13 through #24 indirect address register 0300h: rhpp sts-1/stm- 0 #25 through #36 indirect address register 0380h: rhpp sts-1/stm-0 #37 through #48 indirect address ........................................................................................................... .............200
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use viii register 0201h: rhpp sts-1/stm-0 #1 through #12 indirect data register 0281h: rhpp sts-1/stm-0 #13 through #24 indirect data register 0301h: rhpp sts-1/stm-0 #25 through #36 indirect data register 0381h: rhpp sts-1/stm-0 #37 through #48 indirect data .................................................................................................................. .....................202 register 0208h, 0210h, 0218h, 0220h, 0228h, 0230h, 0238h, 0240h, 0248h, 0250h, 0258h, 0260h register 0288h, 0290h, 0298h, 02a0h, 02a8h, 02b0h, 02b8h, 02c0h, 02c8h, 02d0h, 02d8h, 02e0h register 0308h, 0310h, 0318h, 0320h, 0328h, 0330h, 0338h, 0340h, 0348h, 0350h, 0358h, 0360h register 0388h, 0390h, 0398h, 03a0h, 03a8h, 03b0h, 03b8h, 03c0h, 03c8h, 03d0h, 03d8h, 03e0h: rhpp sts-1/stm-0 #n (where n=1 to 48) pointer interpreter status 203 register 0209h, 0211h, 0219h, 0221h, 0229h, 0231h, 0239h, 0241h, 0249h, 0251h, 0259h, 0261h register 0289h, 0291h, 0299h, 02a1h, 02a9h, 02b1h, 02b9h, 02c1h, 02c9h, 02d1h, 02d9h, 02e1h register 0309h, 0311h, 0319h, 0321h, 0329h, 0331h, 0339h, 0341h, 0349h, 0351h, 0359h, 0361h register 0389h, 0391h, 0399h, 03a1h, 03a9h, 03b1h, 03b9h, 03c1h, 03c9h, 03d1h, 03d9h, 03e1h: rhpp sts-1/stm-0 #n (where n=1 to 48) pointer interpreter interrupt enable 205 register 020ah, 0212h, 021ah, 0222h, 022ah, 0232h, 023ah, 0242h, 024ah, 0252h, 025ah, 0262h register 028ah, 0292h, 029ah, 02a2h, 02aah, 02b2h, 02bah, 02c2h, 02cah, 02d2h, 02dah, 02e2h register 030ah, 0312h, 031ah, 0322h, 032ah, 0332h, 033ah, 0342h, 034ah, 0352h, 035ah, 0362h register 038ah, 0392h, 039ah, 03a2h, 03aah, 03b2h, 03bah, 03c2h, 03cah, 03d2h, 03dah, 03e2h: rhp p sts-1/stm-0 #n (where n=1 to 48) pointer interpreter interrupt status 207 register 020b: rhpp sts-1/stm-0 #1 error monitor status ...............................................209 register 020c: rhpp sts-1/stm-0 #1 error monitor interrupt enable ........................211 register 020d: rhpp sts-1/stm-0 #1 error monitor interrupt status .........................213 register 020e: rhpp sts-1/stm-0 #1 path bip error counter ............................................215 register 020f: rhpp sts-1/stm-0 #1 path rei error counter ............................................216 indirect register 00h: rhpp pointer interpreter configuration ...............................217 indirect register 01h: rhpp error monitor configuration...........................................219 indirect register 02h: rhpp pointer value and erdi..........................................................222 indirect register 03h: rhpp captured and accepted psl................................................223 indirect register 04h: rhpp expected psl and pdi ..............................................................224
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use ix indirect register 05h: rhpp gpo and other status............................................................225 register 0400h: thpp sts-1/stm-0 #1 through #12 indirect address register 0480h: thpp sts-1/stm-0 #13 through #24 indirect a ddress register 0500h: thpp sts-1/stm-0 #25 through #36 indirect address register 0580h: thpp sts-1/stm-0 #37 through #48 indirect address ............................................................................................................... ................227 register 0401h: thpp sts-1/stm-0 #1 through #12 indirect data register 0481h: thpp sts-1/stm-0 #13 through #24 indirect data register 0501h: thpp sts-1/stm-0 #25 through #36 indirect data register 0581h: thpp sts-1/stm-0 #37 through #48 indirect data .................................................................................................................. .....................229 register 0402: thpp payload configuration ..........................................................................230 indirect register 00h: thpp control register ....................................................................231 indirect register 01h: thpp source and pointer control register ..........................233 indirect register 02h: thpp current pointer register ...................................................235 indirect register 03h: thpp arbitrary pointer register ................................................236 indirect register 05h: thpp b3 mask and fixed stuff byte..............................................238 indirect register 06h: thpp transmit c2 and j1....................................................................239 indirect register 07h: thpp transmit h4 mask and g1 .......................................................240 indirect register 08h: thpp transmit f2 and z3....................................................................241 indirect register 09h: thpp transmit z4 and z5....................................................................242 register 0600h: rsvca indirect address .................................................................................243 register 0601h: rsvca indirect data .........................................................................................245 register 0603h: rsvca positive justification interrupt status ...................................248 register 0604h: rsvca negative justification interrupt status..................................249 register 0605h: rsvca fifo overflow interrupt status ..................................................250 register 0606h: rsvca fifo underflow interrupt status ...............................................251 indirect register 00h: rsvca pointer justification interrupt enable .....................252 indirect register 01h: rsvca fifo interrupt enable.........................................................253
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use x indirect register 02h: rsvca positive justifications performance monitor ........254 indirect register 03h: rsvca negative justifications performance monitor ......255 indirect register 04h: rsvca diagnostic/configuration.................................................256 register 0680h: tsvca indirect address..................................................................................258 register 0601h: tsvca indirect data..........................................................................................26 0 register 0603h: tsvca positive justification interrupt status....................................261 register 0604h: tsvca negative justification interrupt status ..................................262 register 0605h: tsvca fifo overflow interrupt status ..................................................263 register 0606h: tsvca fifo underflow interrupt status................................................264 indirect register 00h: tsvca pointer justification interrupt enable .....................265 indirect register 01h: tsvca fifo interrupt enable .........................................................266 indirect register 02h: tsvca positive justifications performance monitor ........267 indirect register 03h: tsvca negative justifications performance monitor.......268 indirect register 04h: tsvca diagnostic/configuration .................................................269 register 0700h: rttp path indirect address ..........................................................................271 register 0701h: rttp path indirect data ..................................................................................273 register 0702h: rttp path trace unstable status..............................................................274 register 0703h: rttp path trace unstable interrupt enable .......................................275 register 0704h: rttp path trace unstable interrupt status ........................................276 register 0705h: rttp path trace mismatch status ..............................................................277 register 0706h: rttp path trace mismatch interrupt enable .......................................278 register 0707h: rttp path trace mismatch interrupt status ........................................279 indirect register 00h: rttp path trace configuration....................................................280 indirect register 40h to 7fh: rttp path captured trace ................................................282
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use xi indirect register 80h to bfh: rttp path accepted trace................................................283 indirect register c0h to ffh: rttp path expected trace ................................................284 register 0708h: tttp path indirect address ..........................................................................285 register 0709h: tttp path indirect data ..................................................................................287 indirect register 00h: tttp path trace configuration ....................................................288 indirect register 40h to 7fh: tttp path trace......................................................................289 register 0720h: sarc indirect address ...................................................................................290 register 0722h: sarc section configuration........................................................................291 register 0723h: sarc section salm enable............................................................................292 register 0724h: sarc section rlaisins enable .....................................................................295 register 0725h: sarc section tlrdiins enable .....................................................................296 register 0728h: sarc path configuration ..............................................................................297 register 0729h: sarc path ralm enable ..................................................................................299 register 072a: sarc path rpaisins enable ..............................................................................300 register 0730h: sarc lop pointer status................................................................................301 register 0731h: sarc lop pointer interrupt enable .........................................................302 register 0732h: sarc lop pointer interrupt status ..........................................................303 register 0733h: sarc ais pointer status .................................................................................304 register 0734h: sarc ais pointer interrupt enable ..........................................................305 register 0735h: sarc ais pointer interrupt status ...........................................................306 register 0740h: rcfp configuration .........................................................................................307 register 0741h: rcfp interrupt enable ...................................................................................310 register 0742h: rcfp interrupt indication and status .....................................................312 register 0743h: rcfp minimum packet length........................................................................314
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use xii register 0744h: rcfp maximum packet length ......................................................................315 register 0745h: rcfp lcd count threshold...........................................................................316 register 0746h: rcfp idle cell header and mask ................................................................317 register 0747h: rcfp receive byte/idle cell counter (lsb)............................................319 register 0748h: rcfp receive byte/idle cell counter ......................................................319 register 0749h: rcfp receive byte/idle cell counter (msb) ...........................................319 register 074ah: rcfp packet/cell counter (lsb) ................................................................320 register 074bh: rcfp receive packet/atm cell counter (msb) ......................................320 register 074ch: rcfp receive erred fcs/hcs counter......................................................321 register 074dh: rcfp receive aborted packet counter..................................................322 register 074eh: rcfp receive minimum length packet error counter .....................323 register 074fh: rcfp receive maximum length packet error counter ....................324 register 0750h: tcfp configuration..........................................................................................325 register 0751h: tcfp interrupt indication .............................................................................328 register 0752h: tcfp idle/unassigned atm cell header ...................................................329 register 0753h: tcfp diagnostics............................................................................................... 331 register 0754h: tcfp transmit cell/packet counter (lsb)..............................................333 register 0755h: tcfp transmit cell/packet counter (msb).............................................333 register 0756h: tcfp transmit byte counter (lsb) .............................................................334 register 0757h: tcfp transmit byte counter........................................................................334 register 0758h: tcfp transmit byte counter (msb) ............................................................334 register 0759h: tcfp aborted packet counter....................................................................335 register 0760h: rxsdq fifo reset ............................................................................................... 336 register 0761h: rxsdq fifo interrupt enable......................................................................337
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use xiii register 0763h: rxsdq fifo overflow port and interrupt indication ......................338 register 0764h: rxsdq fifo sop error port and interrupt indication .....................339 register 0765h: rxsdq fifo eop error port and interrupt indication .....................340 register 0768h: rxsdq fifo indirect address.......................................................................341 register 0769h: rxsdq fifo indirect configuration..........................................................343 register 076ah: rxsdq fifo indirect data available threshold..................................345 register 076bh: rxsdq fifo indirect cells and packets count ....................................346 register 076ch: rxsdq fifo cells and packets accepted aggregate count (lsb) ............................................................................................................................... ....................................347 register 076dh: rxsdq fifo cells and packets accepted aggregate count (msb) ............................................................................................................................... ....................................347 register 076eh: rxsdq fifo cells and packets dropped aggregate count ...........348 register 0770h: txsdq fifo reset............................................................................................... .349 register 0771h: txsdq fifo interrupt enable ......................................................................350 register 0773h: txsdq fifo overflow port and interrupt indication ......................351 register 0774h: txsdq fifo sop error port and interrupt indication......................352 register 0775h: txsdq fifo eop error port and interrupt indication......................353 register 0778h: txsdq fifo indirect address .......................................................................354 register 0779h: txsdq fifo indirect configuration ..........................................................356 register 077ah: txsdq fifo indirect data and buffer available thresholds .......358 register 077bh: txsdq fifo indirect cells and packets count ....................................360 register 077ch: txsdq fifo cells and packets accepted aggregate count (lsb) ............................................................................................................................... ....................................361 register 077dh: txsdq fifo cells and packets accepted aggregate count (msb) ............................................................................................................................... ....................................361 register 077eh: txsdq fifo cells and packets dropped aggregate count............362
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use xiv register 0780h: rxphy configuration.......................................................................................363 register 0781h: rxphy interrupt status .................................................................................364 register 0782h: rxphy interrupt enable ................................................................................365 register 0783h: rxphy indirect burst size .............................................................................366 register 0784h: rxphy calendar length.................................................................................368 register 0785h: rxphy calendar indirect address data .................................................369 register 0786h: rxphy data type field......................................................................................371 register 0788h: txphy configuration .......................................................................................372 register 0789h: txphy interrupt status..................................................................................374 register 078ah: txphy interrupt enable ................................................................................375 register 078bh: txphy data type field .....................................................................................376 register 0790h: sirp configuration timeslot .......................................................................377 register 079ch: sirp configuration ..........................................................................................380 register 0800h: prgm indirect address...................................................................................382 register 0810h: prgm aux 2 indirect address .......................................................................382 register 0820h: prgm aux 3 indirect address .......................................................................382 register 0830h: prgm aux 4 indirect address .......................................................................382 register 0801h: prgm indirect data...........................................................................................38 4 register 0811h: prgm aux 2 indirect data................................................................................384 register 0821h: prgm aux 3 indirect data ...............................................................................384 register 0831h: prgm aux 4 indirect data ...............................................................................384 register 0802h: prgm generator payload configuration ..............................................385 register 0812h: prgm aux 2 generator payload configuration...................................385 register 0822h: prgm aux 3 generator payload configuration...................................385
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use xv register 0832h: prgm aux 4 generator payload configuration...................................385 register 0803h: prgm monitor payload configuration register ................................386 register 0813h: prgm aux 2 monitor payload configuration ........................................386 register 0823h: prgm aux 3 monitor payload configuration ........................................386 register 0833h: prgm aux 4 monitor payload configuration ........................................386 register 0804h: prgm monitor byte error interrupt status ........................................387 register 0814h: prgm aux 2 monitor byte error interrupt status ............................387 register 0824h: prgm aux 3 monitor byte error interrupt status ............................387 register 0834h: prgm aux 4 monitor byte error interrupt status.............................387 register 0805h: prgm monitor byte error interrupt enable .......................................388 register 0815h: prgm aux 2 monitor byte error interrupt enable............................388 register 0825h: prgm aux 3 monitor byte error interrupt enable............................388 register 0835h: prgm aux 4 monitor byte error interrupt enable............................388 register 0806h: monitor b1/e1 bytes interrupt status ....................................................389 register 0807h: monitor b1/e1 bytes interrupt enable....................................................390 register 0808h: monitor b1/e1 bytes status ..........................................................................391 register 0809h: prgm monitor synchronization interrupt status.............................392 register 0819h: prgm aux 2 monitor synchronization interrupt status .................392 register 0829h: prgm aux 3 monitor synchronization interrupt status .................392 register 0839h: prgm aux 4 monitor synchronization interrupt status .................392 register 080ah: prgm monitor synchronization interrupt enable ...........................393 register 081ah: prgm aux 2 monitor synchronization interrupt enable................393 register 082ah: prgm aux 3 monitor synchronization interrupt enable................393 register 083ah: prgm aux 4 monitor synchronization interrupt enable................393
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use xvi register 080bh: prgm monitor synchronization status ..................................................394 register 081bh: prgm aux 2 monitor synchronization status ......................................394 register 082bh: prgm aux 3 monitor synchronization status ......................................394 register 083bh: prgm aux 4 monitor synchronization status ......................................394 indirect register 0800h: prgm monitor timeslot configuration page......................395 indirect register 0801h: prgm monitor prbs[22:7] accumulator page.......................397 indirect register 0802h: prgm monitor prbs[6:0] accumulator page.........................397 indirect register 0803h: prgm monitor b1/e1 value page ................................................398 indirect register 0804h: prgm monitor error count page ............................................399 indirect register 0805h: prgm monitor received b1/e1 bytes page.............................400 indirect register 0808h: prgm generator timeslot configuration page ................401 indirect register 0809h : prgm generator prbs[22:7] accumulator page................403 indirect register 080ah: prgm generator prbs[6:0] accumulator page ..................403 indirect register 080bh: prgm generator b1/e1 value page..........................................404 register 0840h: r8td aps1 control and status ....................................................................405 register 0848h: r8td aps2 control and status ....................................................................405 register 0850h: r8td aps3 control and status ....................................................................405 register 0858h: r8td aps4 control and status ....................................................................405 register 0841h: r8td aps1 interrupt status ..........................................................................408 register 0849h: r8td aps2 interrupt status ..........................................................................408 register 0851h: r8td aps3 interrupt status ..........................................................................408 register 0859h: r8td aps4 interrupt status ..........................................................................408 register 0842h: r8td aps1 line code violation count .......................................................410 register 084ah: r8td aps2 line code violation count .......................................................410
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use xvii register 0852h: r8td aps3 line code violation count .......................................................410 register 085ah: r8td aps4 line code violation count .......................................................410 register 0843h: r8td aps1 analog control 1 ........................................................................411 register 084bh: r8td aps2 analog control 1........................................................................411 register 0853h: r8td aps3 analog control 1 ........................................................................411 register 085bh: r8td aps4 analog control 1........................................................................411 register 0844h: r8td aps1 analog control 2 ........................................................................412 register 084ch: r8td aps2 analog control 2........................................................................412 register 0854h: r8td aps3 analog control 2 ........................................................................412 register 085ch: r8td aps4 analog control 2........................................................................412 register 0860h: t8te aps1 control and status.....................................................................413 register 0868h: t8te aps2 control and status.....................................................................413 register 0870h: t8te aps3 control and status.....................................................................413 register 0878h: t8te aps4 control and status.....................................................................413 register 0861h: t8te aps1 interrupt status...........................................................................415 register 0869h: t8te aps2 interrupt status...........................................................................415 register 0871h: t8te aps3 interrupt status...........................................................................415 register 0879h: t8te aps4 interrupt status...........................................................................415 register 0862h: t8te aps1 telecombus mode #1 ....................................................................416 register 086ah: t8te aps2 telecombus mode #1 ...................................................................416 register 0872h: t8te aps3 telecombus mode #1 ....................................................................416 register 087ah: t8te aps4 telecombus mode #1 ...................................................................416 register 0863h: t8te aps1 telecombus mode #2 ....................................................................417 register 086bh: t8te aps2 telecombus mode #2 ...................................................................417
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use xviii register 0873h: t8te aps3 telecombus mode #2 ....................................................................417 register 087bh: t8te aps4 telecombus mode #2 ...................................................................417 register 0864h: t8te aps1 test pattern ...................................................................................418 register 086ch: t8te aps2 test pattern...................................................................................418 register 0874h: t8te aps3 test pattern ...................................................................................418 register 087ch: t8te aps4 test pattern...................................................................................418 register 0865h: t8te aps1 analog control............................................................................419 register 086dh: t8te aps2 analog control ...........................................................................419 register 0875h: t8te aps3 analog control............................................................................419 register 087dh: t8te aps4 analog control ...........................................................................419 register 0866h: t8te aps1 dtb bus .............................................................................................. 421 register 086eh: t8te aps2 dtb bus.............................................................................................. 421 register 0876h: t8te aps3 dtb bus .............................................................................................. 421 register 087eh: t8te aps4 dtb bus.............................................................................................. 421 register 0880h-0883h: rfclk dll reserved .............................................................................422 register 0884h-0887h: tfclk dll reserved..............................................................................423 register 0888h: cstr control................................................................................................... ...424 register 0889h: cstr interrupt enable and csu lock status .......................................425 register 088ah: cstr csu lock interrupt indication ........................................................426 register 088bh: cstr csu lock interrupt indication ........................................................427 register 0890h-0897: s/uni-2488 rx stsi reserved ..................................................................428 register 0898h-089f: s/uni-2488 tx stsi reserved ..................................................................429
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use xix list of tables table 1: plm-p, uneq-p and pdi-p defects declaration ..........................................................60 table 2: expected pdi defect based on pdi and pdi range values ...................................61 table 3: byte destuffing ...................................................................................................... ............69 table 4: toh insertion priority ................................................................................................ ......73 table 5: z0/national growth bytes definition for row #1 ..................................................75 table 6: byte stuffing ........................................................................................................ ...............78 table 7: register memory map ................................................................................................... .....83 table 8 cru mode control ....................................................................................................... ......123 table 9: functionality of the crc_sel[1:0] register bits ..................................................308 table 10: average sts-x cell period versus lcd integration period ..........................316 table 11: selection of the number of flag bytes ...............................................................325 table 12: crc mode selection .................................................................................................. ....326 table 13: sirp rdi and rei reporting modes............................................................................378 table 14: sirp rdi settings................................................................................................... ..........378 table 15: sirp rdi maintenance................................................................................................ .....379 table 16: sirp rdi priority schemes ........................................................................................... 381 table 17: absolute maximum ratings .........................................................................................449 table 18: d.c characteristics ................................................................................................. .....450 table 19: microprocessor interface read access (figure 26) ......................................453 table 20: microprocessor interface write access (figure 27) ....................................455 table 21: receive system interface timing (figure 28).......................................................457 table 22: transmit system interface timing (figure 29) ....................................................459 table 23: jtag port interface (figure 30) ................................................................................461 table 24: ordering information................................................................................................ ..463 table 25: thermal information .................................................................................................. ...463
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use xx list of figures figure 1: sts-48 (stm-16-16c) atm (utopia level 3) switch port application 11 figure 2: sts-48 (stm-16-16c) packet over sonet (pos-phy level 3) router application 12 figure 3:normal operation 13 figure 4:loopback modes 14 figure 5: aps working 15 figure 6: aps protect 16 figure 7: typical sts-48c (stm-16c) jitter tolerance 50 figure 8: sts-48c (stm-16-16c) on rtoh 53 figure 9: pointer interpretation state diagram 55 figure 10: concatenation pointer interpretation state diagram 58 figure 11: pointer generation state diagram 64 figure 12: cell delineation state diagram 66 figure 13: ppp/hdlc over sonet frame format 68 figure 14: crc decoder 69 figure 15: sts-48c (stm-16-16c) on ttoh 73 figure 16: crc generator 78 figure 17: generic lvds link block diagram 430 figure 18 atm mapping 433 figure 19 packet over sonet mapping 434 figure 20: a 52 byte atm data structure 438 figure 21: a 63 byte packet data structure 438 figure 22 single-phy utopia level 3 receive functional timing 441 figure 23 single-phy utopia level 3 transmit functional timing 442 figure 24 single phy pos-phy level 3 receive functional timing 444 figure 25 single phy pos-phy level 3 transmit functional timing 445 figure 26: intel microprocessor interface read timing 454 figure 27: intel microprocessor interface write timing 455 figure 28: receive system interface timing diagram 458 figure 29: transmit system interface timing 460 figure 30: jtag port interface timing 462
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 1 1 features 1.1 general ? single chip atm and pos user-network interface operating at 2488.32 mbit/s. ? implements the atm forum user network interface specification and the atm physical layer for broadband isdn according to ccitt recommendation i.432. ? implements the point-to-point protocol (ppp) over sonet/sdh specification according to rfc 2615(1619)/1662 of the ppp working group of the internet engineering task force (ietf). ? processes bit-serial 2488.32 mbit/s sts-48 (stm-16-16c) data streams with on-chip clock and data recovery and clock synthesis. ? complies with bellcore gr-253-core jitter tolerance, jitter transfer and intrinsic jitter criteria. ? provides termination for sonet section, line and path overhead or sdh regenerator section, multiplexer section and high order path overhead. ? provides utopia level 3 32-bit wide system interface (clocked up to 104 mhz) with parity support for atm applications. ? provides saturn pos-phy level 3 32-bit system interface (clocked up to 104 mhz) for packet over sonet (pos), or atm applications. ? supports line loopback from the line side receive stream to the transmit stream and diagnostic loopback from the line side transmit stream to the line side receive stream interface. ? provides support for automatic protection switching via a 4-bit lvds 777.76 mhz port. ? provides a standard 5 signal ieee 1149.1 jtag test port for boundary scan board test purposes. ? provides a generic 16-bit microprocessor bus interface for configuration, control, and status monitoring. ? low power 1.8v cmos core logic with 3.3v cmos/ttl compatible digital inputs and digital outputs. pecl inputs and outputs are 3.3v compatible. ? industrial temperature range (-40c to +85c). ? 416 pin ubga package.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 2 1.2 sonet section and line / sdh regenerator and multiplexer section ? frames to the sonet/sdh receive stream and inserts the framing bytes (a1, a2) and the section trace byte (j0) into the transmit stream; descrambles the received stream and scrambles the transmit stream. ? calculates and compares the bit interleaved parity (bip) error detection codes (b1, b2) for the receive stream. calculates and inserts b1 and b2 in the transmit stream. accumulates near end errors (b1, b2) and far end errors (m1) and inserts line remote error indications (rei) into the m1 byte based on received b2 errors. ? detects signal degrade (sd) and signal fail (sf) threshold crossing alarms based on received b1 errors. ? extracted and optionally inserts on dedicated pins the sonet/sdh transport overhead for an sts- 48c/stm-16c frame. ? extracts and serializes on dedicated pins the data communication channels (d1-d3, d4-d12) and inserts the corresponding signals into the transmit stream. ? extracts and filters the automatic protection switch (aps) channel (k1, k2) bytes into internal registers. inserts the aps channel into the transmit stream. ? extracts and filters the synchronization status message (s1) byte into an internal register for the receive stream. inserts the synchronization status message (s1) byte into the transmit stream. ? extracts a 64 byte (bellcore compatible) or 16 byte (itu compatible) section trace (j0) message using an internal register bank for the receive stream. detects an unstable message or mismatch message with an expected message. provides access to the accepted message via the microprocessor port. inserts a 64 byte or 16 byte section trace (j0) message using an internal register bank for the transmit stream. ? detects loss of signal (los), out of frame (oof), loss of frame (lof), line remote defect indication (rdi-l), line alarm indication signal (ais-l), and protection switching byte failure alarms on the receive stream. ? configurable to force line ais in the transmit stream. ? provides automatic transmit line rdi insertion following detection of various received alarms (los, lof, lais, sd, sf, stim, stiu). ? provides automatic drop bus line ais insertion following detection of various received alarms (los, lof, lais, sd, sf, stim, stiu). ? support automatic protection switching (aps) via a serial 4x777.76 lvds mate protection port.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 3 1.3 sonet path / sdh high order path ? interprets the received payload pointer (h1, h2) and extracts the sts-48c/stm-16c synchronous payload envelope and path overhead. ? detects loss of pointer (lop), path alarm indication signal (pais) and path (normal and enhanced) remote defect indication (rdi) for the receive stream. optionally inserts path alarm indication signal (pais) and path remote defect indication (rdi) in the transmit stream. ? extracts and insert the entire sonet/sdh path overhead to and from dedicated pins. the path overhead bytes may be sourced from internal registers or from bit serial path overhead input stream. path overhead insertion may also be disabled. ? extracts the received path payload label (c2) byte into an internal register and detects for payload label unstable (plu), payload label mismatch (plm), payload unequipped (uneq) and payload defect indication (pdi). inserts the path payload label (c2) byte from an internal register for the transmit stream. ? extracts a 64 byte or 16 byte path trace (j1) message using an internal register bank for the receive stream. detects an unstable message or mismatch message with an expected message. provides access to the captured, accepted and expected message via the microprocessor port. inserts a 64 byte or 16 byte path trace (j1) message using an internal register bank for the transmit stream. ? detects received path bip-8 and counts received path bip-8 errors for performance monitoring purposes. bip-8 errors are selectable to be treated on a bit basis or block basis. optionally calculates and inserts path bip-8 error detection codes for the transmit stream. ? counts received path remote error indications (rei?s) for performance monitoring purposes. optionally inserts the path rei count into the path status byte (g1) based on bit or block bip-8 errors detected in the receive path. reporting of bip-8 errors is on a bit or block basis independent of the accumulation of bip-8 errors. ? provides automatic transmit path rdi and path enhanced rdi insertion following detection of various received alarms (lais, lop, lopcon, pais, paiscon, ptim, ptiu, plm, plu, uneq, pdi). 1.4 the receive atm processor ? extracts atm cells from the received sts-48c/stm16-16c channel payloads using atm cell delineation. ? provides atm cell payload de-scrambling. ? performs header check sequence (hcs) error detection and correction, and idle/unassigned cell filtering. ? detects out of cell delineation (ocd) and loss of cell delineation (lcd) alarms.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 4 ? counts number of received cells, idle cells, erred cells and dropped cells. ? provides utopia level 3 and pos-phy level 3 32-bit wide datapath interfaces (clocked up to 104 mhz) with parity support to read extracted cells from an internal 8 cell fifo buffer. 1.5 the receive pos processor ? supports packet based link layer protocols using byte synchronous hdlc framing. ? performs self-synchronous pos data de-scrambling on the received sts-48c/stm16c-16c payloads using the x 43 +1 polynomial. ? performs flag sequence detection and terminates the received pos frames. ? performs frame check sequence (fcs) validation for crc-ccitt and crc-32 polynomials. ? performs control escape de-stuffing or byte de-stuffing of the pos stream. ? detects packet abort sequence. ? checks for minimum and maximum packet lengths. optionally deletes short packets and marks those exceeding the maximum length as erred. ? permits fcs stripping on the pos-phy output data stream. ? provides a saturn pos-phy level 3 compliant 32-bit datapath interface (clocked up to 104 mhz) with parity support to read packet data from an internal 256 byte fifo buffer. 1.6 the transmit atm processor ? provides idle/unassigned cell insertion. ? optionally provides hcs generation/insertion, and atm cell payload scrambling. ? counts the number of transmitted cells. ? provides utopia level 3 and pos-phy level 3 32-bit wide datapath interfaces (clocked up to 104 mhz) with parity support for writing cells into an internal channel fifo. 1.7 the transmit pos processor ? supports any packet based link layer protocol using byte synchronous and bit synchronous framing like ppp, hdlc and frame relay. ? performs self-synchronous pos data scrambling using the 1+x 43 polynomial.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 5 ? encapsulates packets within a pos/hdlc frame. ? performs flag sequence insertion. ? performs byte stuffing for transparency processing. ? optionally performs frame check sequence generation using the crc-ccitt and crc-32 polynomials. ? aborts packets under the direction of the host or when the fifo underflows. ? provides a saturn pos-phy level 3 compliant 32-bit wide datapath (clocked up to 104 mhz) with parity support to an internal fifo buffer.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 6 2 applications ? atm/ multi-service enterprise, access, edge and core switches ? packet over sonet interfaces for access, edge and core routers ? sonet/sdh add/drop multiplexers and terminal multiplexers with data processing capabilities ? dwdm optical networking equipment requiring sonet/sdh capabilities ? network interface cards and uplinks
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 7 3 references ? bell communications research - gr-253-core ?sonet transport systems: common generic criteria?, issue 2 revision 2, january 1999. ? bell communications research - gr-436-core ?digital network synchronization plan?, issue 1 revision 1, june 1996.. ? ansi - t1.105-1995, ?synchronous optical network (sonet) ? basic description including multiplex structure, rates, and formats?, 1995. ? ansi t1.107 - 1995, "digital hierarchy - formats specifications". ? ansi t1.107a - 1990, "digital hierarchy - supplement to formats specifications (ds3 format applications)". ? ansi t1.627 - 1993, "broadband isdn - atm layer functionality and specification". ? ets 300 417-1-1, "generic functional requirements for synchronous digital hierarchy (sdh) equipment", january, 1996. ? itu-t recommendation g.703 - "physical/electrical characteristics of hierarchical digital interfaces", 1991. ? itu-t recommendation g.704 - "general aspects of digital transmission systems; terminal equipment - synchronous frame structures used at 1544, 6312, 2048, 8488 and 44 736 kbit/s hierarchical levels", july 1995. ? itu, recommendation g.707 - "network node interface for the synchronous digital hierarchy", 1996. ? itu recommendation g781, ?structure of recommendations on equipment for the synchronous design hierarchy (sdh)?, january 1994. ? itu, recommendation g.783 - "characteristics of synchronous digital hierarchy (sdh) equipment functional blocks", 1996. ? itu recommendation i.432, ?isdn user network interfaces?, 1993. ? itu recommendation i.432, ?isdn user network interfaces?, march 93. ? atm forum - atm user-network interface specification, v3.1, october, 1995. ? atm forum ? str-phy-ul3-01.00, ?utopia level 3?, april, 1999.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 8 ? ietf network working group ? rfc-1619, ?point to point protocol (ppp) over sonet/sdh specification?, may 1994. ? ietf network working group ? rfc-1661, ?the point to point protocol (ppp)?, july, 1994. ? ietf network working group ? rfc-1662, ?ppp in hdlc like framing?, july 1994. ? ietf network working group ? rfc-2615, ?point to point protocol (ppp) over sonet/sdh?, june 1999. ? pmc-980495, ?saturn compatible interface for packet over sonet physical layer and link layer devices (level 3)?, issue 3, dec. 2, 1998.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 9 4 definitions the following table defines the abbreviations for the s/uni-2488. atm asynchronous transfer mode csu clock synthesis unit dru data recovery unit fcs frame check sequence fifo first-in-first-out storage element hcs header check sequence lvds low voltage differential signaling nni network-to-network interface pos packet over sonet prgm prbs generator and monitor rcfp receive cell and frame processor block rhpp receive high order path processor rrmp receive regenerator multiplexer processor rttp received tail trace processor rxsdq receive scalable data queue fifo rxsif receive slave interface (ul3 or pos l3) srli sonet/sdh receive line interface stli sonet/sdh transmit line imterface stsi sonet/sdh time slot interchange svca sonet/sdh virtual container aligner tcfp transmit cell and frame processor block thpp transmit high order path processor trmp transmit regenerator multiplexer processor tttp transmit tail trace processor txsif transmit slave interface (ul3 or pos l3)
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 10 5 application examples the pm5381 s/uni-2488 is applicable to equipment implementing asynchronous transfer mode (atm) user-network interfaces (uni), atm network-network interfaces (nni), as well as packet over sonet (pos) interfaces. the pos interface can support several packet based protocols, including the point-to-point protocol (ppp). the s/uni-2488 may find application at either end of switch-to-switch links, router to router links, switch to router links or switch-to-terminal links, in public and privite wide area networks (wan). the s/uni-2488 provides a comprehensive feature set as well as full compliance to wan synchronization requirements. the s/uni-2488 performs the mapping of either atm cells or pos frames into the sonet/sdh sts-48 (stm-16-16c) synchronous payload envelope (spe) and processes applicable sonet/sdh section, line and path overheads. in a typical sts-48 (stm-16-16c) atm application, the s/uni-2488 performs clock and data recovery in the receive direction and clock synthesis in the transmit direction of the line interface. on the system side, the s/uni-2488 interfaces directly with atm layer processors and switching or adaptation functions using a utopia level 3 compliant 32-bit (clocked up to 104 mhz) synchronous fifo style interface. an application with a utopia level 3 system side interface is shown in figure 1. the initial configuration and ongoing control and monitoring of the s/uni- 2488 are normally provided via a generic microprocessor interface.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 11 figure 1: sts-48 (stm-16-16c) atm (utopia level 3) switch port application pm5381 s/uni-2488 tfclk tenb tca tsoc tprty tdat[31:0] rfclk renb rca rsoc rprty rdat[31:0] optical transceiver pm7325 s/uni-atlas3200 atm layer device txclk txenb txclav txsoc txprty txdata[31:0] rxclk rxenb rxclav rxsoc rxprty rxdata[31:0] rxd+/- sd txd+/- 0 posl3_ul3b
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 12 in a typical packet over sonet application (i.e. using the ppp protocol) the s/uni-2488 performs clock and data recovery in the receive direction and clock synthesis in the transmit direction of the line interface. on the system side, the s/uni-2488 interfaces directly with a data link layer processor using a saturn pos-phy level 3 32-bit (clocked up to 104 mhz) synchronous fifo interface over which packets are transferred. the initial configuration and ongoing control and monitoring of the s/uni-2488 are normally provided via a generic microprocessor interface. figure 2: sts-48 (stm-16-16c) packet over sonet (pos-phy level 3) router application pm5381 s/uni-2488 tfclk tenb dtp a tsop tprty tdat[31:0] rfclk renb rsx rsop rprty rdat[31:0] link layer device tfclk tenb dtpa tsop tprty tdat[31:0] rfclk renb rsx rsop rprty rdat[31:0] optical transceiver rxd+/- sd txd+/- tmod[1:0] tmod[1:0] teop teop terr terr rmod[1:0] rmod[1:0] reop reop rerr rerr rval rval 1 posl3_ul3b
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 13 6 block diagram figure 3:normal operation rclk oof rrmp (4) sarc thpp (4) rttp (1) rttp (1) tttp (1) srli (1) trmp (4) stli (1) sber (1) sd rtoh rpoh rpohen b3e tohclk tohfp rohclk rohfp ttoh ttohen tpoh tpohen tpohrdy tttp (1) c0 c1 jtag tdi tdo trstb tms tck analog c2 c3 res resk atp[3:0] tclk rhpp (4) ralm pgmtclk pgmrclk tx line i/f rx line i/f refclk+/- txd+/- rxd+/- rcfp (1) rxsdq fifo (1) rxphy (1) rdat[31:0] rprty rsoc/rsop rca/rval reop rfclk renb rmod[1:0] rsx rerr tcfp (1) txsdq fifo (1) txphy (1) tdat[31:0] tprty tsoc/tsop tca/dtpa teop tfclk tenb tmod[1:0] terr microprocessor d[15:0] csb a[13:0] ale wrb intb rdb apso+/-[4:1] svca (4) rxlv (4) dru (4) r8tb (4) apsi+/-[4:1] apsifp d8e (4) apiso (4) txlv (4) csu txlvref apsofp apsmode sirp (1) stsi (1) stsi (1) rstb prgm (4) salm posl3_ul3b
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 14 figure 4:loopback modes rclk oof rrmp (4) sarc thpp (4) rttp (1) rttp (1) tttp (1) srli (1) trmp (4) stli (1) sber (1) sd rtoh rpoh rpohen b3e tohclk tohfp rohclk rohfp ttoh ttohen tpoh tpohen tpohrdy tttp (1) c0 c1 jtag tdi tdo trstb tms tck analog c2 c3 res resk atp[3:0] tclk rhpp (4) ralm pgmtclk pgmrclk tx line i/f rx line i/f refclk+/- txd+/- rxd+/- rcfp (1) rxsdq fifo (1) rxphy (1) rdat[31:0] rprty rsoc/rsop rca/rval reop rfclk renb rmod[1:0] rsx rerr tcfp (1) txsdq fifo (1) txphy (1) tdat[31:0] tprty tsoc/tsop tca/dtpa teop tfclk tenb tmod[1:0] terr microprocessor d[15:0] csb a[13:0] ale wrb intb rdb apso+/-[4:1] svca (4) rxlv (4) dru (4) r8tb (4) apsi+/-[4:1] apsifp d8e (4) apiso (4) txlv (4) csu txlvref apsofp apsmode sirp (1) stsi (1) stsi (1) rstb prgm (4) salm posl3_ul3b line loopback (slle=1) serial diagnostic loopback (sdle=1) or parallel diagnostic loopback (pdlb=1)
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 15 figure 5: aps working rclk oof rrmp (4) sarc thpp (4) rttp (1) rttp (1) tttp (1) srli (1) trmp (4) stli (1) sber (1) sd rtoh rpoh rpohen b3e tohclk tohfp rohclk rohfp ttoh ttohen tpoh tpohen tpohrdy tttp (1) c0 c1 jtag tdi tdo trstb tms tck analog c2 c3 res resk atp[3:0] tclk rhpp (4) ralm pgmtclk pgmrclk tx line i/f rx line i/f refclk+/- txd+/- rxd+/- rcfp (1) rxsdq fifo (1) rxphy (1) rdat[31:0] rprty rsoc/rsop rca/rval reop rfclk renb rmod[1:0] rsx rerr tcfp (1) txsdq fifo (1) txphy (1) tdat[31:0] tprty tsoc/tsop tca/dtpa teop tfclk tenb tmod[1:0] terr microprocessor d[15:0] csb a[13:0] ale wrb intb rdb apso+/-[4:1] svca (4) rxlv (4) dru (4) r8tb (4) apsi+/-[4:1] apsifp d8e (4) apiso (4) txlv (4) csu txlvref apsofp apsmode sirp (1) stsi (1) stsi (1) rstb prgm (4) salm posl3_ul3b aps failover (mode=10, apsmode=1) from protect mate to protect mate
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 16 figure 6: aps protect rclk oof rrmp (4) sarc thpp (4) rttp (1) rttp (1) tttp (1) srli (1) trmp (4) stli (1) sber (1) sd rtoh rpoh rpohen b3e tohclk tohfp rohclk rohfp ttoh ttohen tpoh tpohen tpohrdy tttp (1) c0 c1 jtag tdi tdo trstb tms tck analog c2 c3 res resk atp[3:0] tclk rhpp (4) ralm pgmtclk pgmrclk tx line i/f rx line i/f refclk+/- txd+/- rxd+/- rcfp (1) rxsdq fifo (1) rxphy (1) rdat[31:0] rprty rsoc/rsop rca/rval reop rfclk renb rmod[1:0] rsx rerr tcfp (1) txsdq fifo (1) txphy (1) tdat[31:0] tprty tsoc/tsop tca/dtpa teop tfclk tenb tmod[1:0] terr microprocessor d[15:0] csb a[13:0] ale wrb intb rdb apso+/-[4:1] svca (4) rxlv (4) dru (4) r8tb (4) apsi+/-[4:1] apsifp d8e (4) apiso (4) txlv (4) csu txlvref apsofp apsmode sirp (1) stsi (1) stsi (1) rstb prgm (4) salm posl3_ul3b aps failover (mode=11, aspmode=0) from working mate to working mate
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 17 7 description the pm5381 s/uni-2488 saturn user network interface is a monolithic integrated circuit that implements sonet/sdh processing, atm mapping and packet over sonet mapping functions at the sts-48 (stm-16-16c) 2488.32 mbit/s rate. the s/uni-2488 receives sonet/sdh streams using a bit serial interface, recovers the clock and data and processes section, line, and path overhead. the s/uni-2488 performs framing (a1, a2), de-scrambling, detects alarm conditions, and monitors section, line, and path bit interleaved parity (b1, b2, b3), accumulating error counts at each level for performance monitoring purposes. line and path remote error indications (m1, g1) are also accumulated. the s/uni-2488 interprets the received payload pointers (h1, h2) and extracts the synchronous payload envelope which carries the received atm cells or pos frames. when used to implement an atm uni or nni, the s/uni-2488 frames to the atm payload using cell delineation. hcs error correction is provided. idle/unassigned cells may be optionally dropped. cells are also dropped upon detection of an uncorrectable header check sequence error. the atm cell payloads are descrambled and are written to a 8-cell fifo buffer. the received cells are read from the fifo using a 32-bit wide utopia level 3 (clocked up to 104 mhz) datapath interface. counts of received atm cell headers that are errored and uncorrectable and those that are errored and correctable are accumulated independently for performance monitoring purposes. when used to implement packet transmission over a sonet/sdh link, the s/uni-2488 extracts packet over sonet (pos) frames from the sonet/sdh synchronous payload envelope. frames are verified for correct construction and size. the control escape characters are removed. the frame check sequence is optionally verified for correctness and the extracted packets are placed in a receive fifo. the received packets are read from the fifo through a 32-bit pos-phy level 3 (clocked up to 104 mhz) system side interface. valid and fcs errored packet counts are provided for performance monitoring. the s/uni-2488 packet over sonet implementation is flexible enough to support several link layer protocols, including hdlc, ppp and frame relay. the s/uni-2488 transmits sonet/sdh streams using a bit serial interface. the s/uni-2488 synthesizes the transmit clock from a 155.52mhz frequency reference and performs framing pattern insertion (a1, a2), scrambling, alarm signal insertion, and creates section, line, and path bit interleaved parity codes (b1, b2, b3) as required to allow performance monitoring at the far end. line and path remote error indications (m1, g1) are also inserted. the s/uni-2488 generates the payload pointer (h1, h2) and inserts the synchronous payload envelope that carries the atm or pos frames. the s/uni-2488 also supports the insertion of a large variety of errors into the transmit stream, such as framing pattern errors, bit interleaved parity errors, and illegal pointers, which are useful for system diagnostics and tester applications.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 18 when used to implement an atm uni or nni, atm cells are written to an internal 8 cell fifo using a 32-bit wide utopia level 3 (clocked up to 104 mhz) datapath interface. idle/unassigned cells are automatically inserted when the internal fifo contains less than one complete cell. the s/uni-2488 provides generation of the header check sequence and scrambles the payload of the atm cells. each of these transmit atm cell processing functions can be enabled or bypassed. when used to implement a packet over sonet/sdh link, the s/uni-2488 inserts pos frames into the sonet/sdh synchronous payload envelope. packets to be transmitted are written into a 256-byte fifo through a 32-bit saturn pos-phy level 3 (clocked up to 104 mhz) system side interface. pos frames are built by inserting the flags, control escape characters and the fcs fields. either the crc-ccitt or crc-32 can be computed and added to the frame. several counters are provided for performance monitoring. no line rate clocks are required directly by the s/uni-2488 as it synthesizes the transmit clock and recovers the receive clock using a 155.52 mhz reference clock. the s/uni-2488 outputs a differential pecl line data (txd+/-). the s/uni-2488 is configured, controlled and monitored via a generic 16-bit microprocessor bus interface. the s/uni-2488 also provides a standard 5 signal ieee 1149.1 jtag test port for boundary scan board test purposes. the s/uni-2488 is implemented in low power, +1.8 volt, cmos technology. it has ttl compatible digital inputs and ttl/cmos compatible digital outputs. high speed inputs and outputs support 3.3v compatible pseudo-ecl (pecl). the s/uni-2488 is packaged in a 416 pin ubga package.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 19 8 pin diagrams tbd
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 20 9 sdpin description 9.1 serial line side interface signals (7) pin name type pin no. function refclk+ refclk- differential pecl input ak10 ak9 the differential reference clock inputs (refclk+/-) provides a jitter-free 155.52 mhz reference clock for both the clock recovery and the clock synthesis circuits. the 8khz frame pulse, apsifp is sampled upon a rising edge transition of refclk+/- (i.e. apsifp is phase-synchronous with refclk+/- ). apsofp is updated upon a rising edge transition of refclk+/- (i.e. apsofp is phase-synchronous with refclk+/-). please refer to the operation section for a discussion of pecl interfacing issues. rxd+ rxd- differential pecl input ak16 ak15 the receive differential data pecl inputs (rxd+/-) contain the nrz bit serial receive stream. the receive clock is recovered from the rxd+/- bit stream. please refer to the operation section for a discussion of pecl interfacing issues. sd ttl input ah24 the receive signal detect ttl input (sd) indicates the presence of valid receive signal power from the optical physical medium dependent device. a logic high indicates the presence of valid data. a logic low indicates a loss of signal. please refer to the operation section for a discussion of interfacing issues txd+ txd- differential pecl output ak13 ak12 the transmit differential data pecl outputs (txd+/-) contain the 2488.32 mbit/s transmit stream. the txd+/- outputs are driven using the synthesized clock from the csu. please refer to the operation section for a discussion of pecl interfacing issues.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 21 9.2 clocks and alarms (7) pin name type pin no. function pgmrclk output ak25 the programmable receive clock (pgmrclk) signal provides timing reference for the receive line interface. pgmrclk is a divided version of the recovered clock. when pgmrclksel register bit is set low, pgmrclk is a nominal 19.44 mhz, 50% duty cycle clock. when pgmrclksel register bit is set to high, pgmrclk is a nominal 8 khz, 50% duty cycle clock. the pgmrclk output can be disabled and held low by programming the pgmrclken bit in the srli pgm clock configuration register. rclk output ag23 the receive clock (rclk) signal provides timing reference for the receive interface. rclk is a nominal 77.76 mhz 50% duty cycle clock. the rclk output can be disabled and held low by programming the rclken bit in the srli clock configuration register. oof and salm are updated on the rising edge of rclk. pgmtclk output ah23 the programmable transmit clock (pgmtclk) signal provides timing reference for the transmit line interface. pgmtclk is a divided version of the recovered clock. when pgmtclksel register bit is set low, pgmtclk is a nominal 19.44 mhz, 50% duty cycle clock. when pgmtclksel register bit is set to high, pgmtclk is a nominal 8 khz, 50% duty cycle clock. the pgmtclk output can be disabled and held low by programming the pgmtclken bit in the stli pgm clock configuration register. tclk output aj24 the transmit clock (tclk) signal provides timing reference for the transmit interface. tclk is a nominal 77.76mhz 50% duty cycle clock. the tclk output can be disabled and held low by programming the tclken bit in the stli pgm clock configuration register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 22 pin name type pin no. function oof output ah27 the active high out of frame (oof) signal indicates when an out of frame condition is declared by the framing block. oof is set high while the framing block is out of frame. an out of frame condition is declared when four consecutive errored framing patterns (a1 and a2 bytes) have been detected. oof is set low while the framing block is in frame. oof is updated on the rising edge of rclk. salm output ag26 the section alarm (salm) signal is set high when an out of frame (oof), loss of signal (los), loss of frame (lof), line alarm indication signal (lais), line remote defect indication (lrdi), section trace identifier mismatch (tim-s), section trace identifier unstable (tiu-s), signal fail (sf) or signal degrade (sd) alarm is detected. each alarm indication can be independently enabled using bits in the s/uni-2488 sarc section salm enable registers. salm is set low when none of the enabled alarms are active. salm is updated on the rising edge of rclk. ralm output ak28 the receive alarm (ralm) signal is a multiplexed output of individual alarms of the receive path. each alarm represents the logical or of the salm, lop-p, ais-p, rdi-p, erdi-p, lopc-p, paisc-p, uneq-p, pslu, pslm, pdi-p, tiu-p, tim- p status of the path. the selection of alarms to be reported is controlled by the s/uni-2488 sarc path ralm enable registers. ralm is updated on the falling edge of rohclk. please refer to the individual alarm interrupt descriptions and functional description section for more details on each alarm. csuclko output ag22 this clock is used for pmc test purposes only. it must be left as a no connect (nc) during the normal mode of operation. csuclki input ak24 this clock is used for pmc test purposes only. it must be tied to vss during the normal mode of operation. cruclko output aj23 this clock is used for pmc test purposes only. it must be left as a no connect (nc) during the normal mode of operation.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 23 9.3 receive section/line/path overhead extraction signals (6) pin name type pin no. function rohclk output v30 the receive overhead clock (rohclk) signal provides timing for the receive section, line and path overhead extraction. rohclk is a nominal 20.736 mhz clock generated by gapping a 25.92 mhz clock. rohclk has a 33% high duty cycle. rohfp, rtoh, rpoh, rpohen, b3e are updated on the falling edge of rohclk. rohfp output u27 the receive overhead frame pulse (rohfp) signal provides timing for the receive section, line and path overhead extraction. rohfp is used to indicate the most significant bit (msb) on rtoh, rpoh and the first possible path bip error on b3e. rohfp can be sample on the rising edge of rohclk. rohfp is updated on the falling edge of rohclk. rtoh output v29 the receive transport overhead (rtoh) signal contains the received transport overhead bytes (a1, a2, j0, z0, b1, e1, f1, d1-d3, h1-h3, b2, k1, k2, d4-d12, z1/s1, z2/m1, and e2) extracted from the incoming stream. rtoh is updated on the falling edge of rohclk. rpoh output v27 the receive path overhead (rpoh) signal contains the received path overhead bytes (j1, b3, c2, g1, f2, h4, z3, z4, and z5) extracted from the sts-48c/stm16c sonet/sdh path overhead the rpohen signal is set high to indicate valid path overhead bytes on rpoh. rpoh is updated on the falling edge of rohclk.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 24 pin name type pin no. function rpohen output v28 the receive path overhead enable (rpohen) signal indicates valid path overhead bytes on rpoh when rpohen signal is set high, the corresponding path overhead byte presented on rpoh is valid. when rpohen is set low, the corresponding path overhead byte presented on rpoh is invalid. rpohen is updated on the falling edge of rohclk. b3e output w29 the bit interleaved parity error (b3e) signal carries the path bip-8 errors detected for the sts-48c sonet payload. b3e is set high for one rohclk clock cycle for each path bip-8 error detected (up to eight errors per path per frame). when bip-8 errors are treated on a block basis, b3e is set high for one rohclk clock cycle for up to eight path bip-8 errors detected (up to one error per path per frame). path bip-8 errors are detected by comparing the extracted path bip-8 byte (b3) with the computed path bip-8 byte of the previous frame. b3e is updated on the falling edge of rohclk. 9.4 transmit section/line/path overhead insertion signals (7) pin name type pin no. function tohclk output aj27 the transmit overhead clock (tohclk) signal provides timing for the transmit section, line and path overhead insertion. tohclk is a nominal 20.736mhz clock generated by gapping a 25.92mhz clock. tohclk has a 33% high duty cycle. tohfp and tpohrdy are updated on the falling edge of tohclk. ttoh, ttohen, tpoh and tpohen are sampled on the rising edge of tohclk.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 25 pin name type pin no. function tohfp output ag25 the transmit overhead frame pulse (tohfp) signal provides timing for the transmit section, line and path overhead insertion. tohfp is used to indicate the most significant bit (msb) on ttoh and tpoh. tohfp is set high when the msb of the: first a1 byte should be present on ttoh. first j1 byte should be present on tpoh. tohfp can be sampled on the rising edge of tohclk. tohfp is updated on the falling edge of tohclk. ttoh input ak27 the transmit transport overhead (ttoh) signal contains the transport overhead bytes (a1, a2, j0, z0, b1, e1, f1, d1-d3, h1-h3, b2, k1, k2, d4-d12, z1/s1, z2/m1, and e2) to be transmitted and the error masks to be applied on b1, b2, h1 and h2. ttoh is sampled on the rising edge of tohclk. ttohen input aj26 the transmit transport overhead insert enable (ttohen) signal controls the insertion of the transmit transport overhead data which is inserted in the outgoing stream. when ttohen is high during the most significant bit of a toh byte on ttoh, the sampled toh byte is inserted into the corresponding transport overhead byte positions (a1, a2, j0, z0, e1, f1, d1-d3, h3, k1, k2, d4-d12, z1/s1, z2/m1, and e2 bytes). when ttohen is low during the most significant bit of a toh byte on ttoh, that sampled byte is ignored and the default values are inserted into these transport overhead bytes. when ttohen is high during the most significant bit of the h1, h2, b1 or b2 toh byte positions on ttoh, the sampled toh byte is logically xor?ed with the associated incoming byte to force bit errors on the outgoing byte. a logic low bit in the ttoh byte allows the incoming bit to go through while a bit set to logic high will toggle the outgoing bit. a low level on ttohen during the msb of the toh byte disables the error forcing for the entire byte. ttohen is sampled on the rising edge of tohclk.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 26 pin name type pin no. function tpoh input ah25 the transmit path overhead (tpoh) signal contains the path overhead bytes (j1, c2, g1, f2, z3, z4, and z5) to be transmitted in the sts-48c sonet path overhead and the error masks to be applied on b3 and h4. a path overhead byte is accepted for transmission when the external source indicates a valid byte (tpohen set high) and the s/uni-2488 indicates ready (tpohrdy set high). the s/uni-2488 will ignore the byte on tpoh when tpohen is set low. the tpohrdy is set low to indicate the s/uni-2488 is not ready, and the byte must be re-presented at the next opportunity. tpoh is sampled on the rising edge of tohclk. tpohrdy output aj25 the transmit path overhead insert ready (tpohrdy) signal indicates if the s/uni-2488 is ready to accept the byte currently on tpoh. tpohrdy is set high during the most significant bit of a poh byte to indicate readiness to accept the byte on the tpoh input. this byte will be accepted if tpohen is also set high. if tpohen is set low, the byte is invalid and is ignored. tpohrdy is set low to indicate that the s/uni-2488 is unable to accept the byte on tpoh, and expects the byte to be re- presented at the next opportunity. tpohrdy is updated on the falling edge of tohclk.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 27 pin name type pin no. function tpohen input ak26 the transmit path overhead insert enable (tpohen) signal controls the insertion of the transmit path overhead data which is inserted in the outgoing stream. tpohen shall be set high during the most significant bit of a poh byte to indicate valid data on the tpoh input. this byte will be accepted for transmission if tpohrdy is also set high. if tpohrdy is set low, the byte is rejected and must be re- presented at the next opportunity. accepted bytes sampled on tpoh are inserted into the corresponding path overhead byte positions (for the j1, c2, g1, f2, z3, z4, and z5 bytes). the byte on tpoh is ignored when tpohen is set low during the most significant bit position. when the byte at the b3 or h4 byte position on tpoh is accepted, it is used as an error mask to modify the corresponding transmit b3 or h4 path overhead byte, respectively. the accepted error mask is xor?ed with the corresponding b3 or h4 byte before it is transmitted. tpohen is sampled on the rising edge of the tohclk.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 28 9.5 system side utopia and pos signals (84) pin name type pin no. function posl3_ ul3b input b19 the utopia/pos interface select (posl3/ul3b) selects between utopia level 3 and pos-phy level 3 mode for the system side interface. when posl3/ul3b is low, the utopia level 3 interface is selected. when high, the pos-phy level 3 interface is selected. the utopia receive fifo read clock (rfclk) signal is used to read atm cells from the receive cell fifo. rfclk is expected to cycle at 104 mhz. rfclk input e28 the pos-phy receive fifo read clock (rfclk ) signal is used to read packet data from the 256 byte packet fifo. rfclk is expected to cycle at 104 mhz. the utopia receive parity (rprty) rprty signal indicates the parity of the rdat bus. the rprty signal indicates the parity on the rdat[31:0] bus. either odd or even parity selection can be selected. rprty is updated on the rising edge of rfclk. rprty output p29 the pos-phy receive parity (rprty) signal indicates the parity of the rdat bus. either odd or even parity can be selected. rprty is updated on the rising edge of rfclk.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 29 pin name type pin no. function the utopia receive cell data (rdat[31:0]) bus carries the atm cell octets that are read from the receive fifo. rdat[31:0] is updated on the rising edge of rfclk. rdat[31] rdat[30] rdat[29] rdat[28] rdat[27] rdat[26] rdat[25] rdat[24] rdat[23] rdat[22] rdat[21] rdat[20] rdat[19] rdat[18] rdat[17] rdat[16] rdat[15] rdat[14] rdat[13] rdat[12] rdat[11] rdat[10] rdat[9] rdat[8] rdat[7] rdat[6] rdat[5] rdat[4] rdat[3] rdat[2] rdat[1] rdat[0] output d30 e29 f28 g27 e30 f29 g28 h27 f30 h28 j27 g30 h29 j28 h30 j29 k28 l27 j30 l28 m27 k30 l29 m28 l30 n27 m29 n28 m30 p27 n30 p28 the pos-phy receive packet data (rdat[31:0]) bus carries the pos packet octets that are read from the receive fifo. the rdat[31:0] signals are valid when rval and renb are asserted. rdat[31:0] is updated on the rising edge of rfclk. renb input u28 the utopia receive read enable (renb) signal is used to initiate reads from the receive fifo. the system may de-assert renb at any time if it is unable to accept more data. a read is not performed and rdat[31:0] does not change when renb is sampled high. when renb is sampled low, the word on the rdat[31:0] bus is read from the receive fifo and rdat[31:0] changes to the next value on the next clock cycle. renb is sampled on the rising edge of rfclk.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 30 pin name type pin no. function renb (continued input u28 the pos-phy receive read enable (renb) signal is used to initiate reads from the receive fifo. during a data transfer, rval must be monitored since it will indicate if the data is valid. the system may deassert renb at any time if it is unable to accept more data. a read is not performed and rdat[31:0] does not change when renb is sampled high. when renb is sampled low, the word on the rdat[31:0] bus is read from the receive fifo and rdat[31:0] changes to the next value on the next clock cycle. renb is sampled on the rising edge of rfclk. the utopia receive start of cell (rsoc) signal marks the start of a cell structure on the rdat[31:0] bus. the first word of the cell structure is present on the rdat[31:0] bus when rsoc is high. rsoc is updated on the rising edge of rfclk. rsoc rsop output r28 the pos-phy receive start of packet (rsop) signal indicates the start of a packet on the rdat[31:0] bus. rsop is set high for the first word of a packet on rdat[31:0]. rsop is updated on the rising edge of rfclk rca output u30 the utopia receive cell available (rca) signal provides direct status indication of when a cell is available in the receive fifo. rca can be configured to de-assert when either zero or four words remain in the fifo. rca will thus transition low on the rising edge of rfclk after payload word 12 or 7 is output on the rdat[31:0] bus depending on the configuration. rca is updated on the rising edge of rfclk.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 31 pin name type pin no. function rval output u30 the pos-phy receive data valid (rval) signal indicates the validity of the receive data signals. when rval is high, the receive signals rdat[31:0], rprty, rsop, reop, rmod[1:0], and rerr are valid. when rval is low, all receive signals are invalid and must be disregarded. rval will be high when valid data is on the rdat[31:0] bus. rval will transition low when the fifo is empty. rval will remain low until a programmable minimum number of bytes exist in the receive fifo. the threshold is configurable. rval is updated on the rising edge of rfclk. rerr the pos-phy receive error (rerr) signal indicates that the current packet is invalid due to an error such as invalid fcs, excessive length or received abort. rerr may only assert when reop is asserted marking the last word of the packet. rerr is only used in pos mode and is updated on the rising edge of rfclk. reop output p30 the pos-phy receive end of packet (reop) signal marks the end of packet on the rdat[31:0] bus. it is legal for rsop to be high at the same time reop is high. reop is set high to mark the last word of the packet presented on the rdat[31:0] bus. when reop is high, rmod[1:0] specifies if the last word has 1, 2, 3, or 4 valid bytes of data. reop is only used for pos operation and is updated on the rising edge of rfclk.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 32 pin name type pin no. function rmod[1] rmod[0] output t28 t29 the pos-phy transmit word modulo (rmod[1:0]) bus indicates the size of the current word when configured for packet mode. during a packet transfer, every word on rdat[31:0] must contain four valid bytes of packet data except at the end of the packet where the word is composed of 1, 2, 3, or 4 valid bytes. the number of valid bytes in this last word is specified by rmod[1:0]. rmod[1:0] = ?00? rdat[31:0] valid rmod[1:0] = ?01? rdat[31:8] valid rmod[1:0] = ?10? rdat[31:16] valid rmod[1:0] = ?11? rdat[31:24] valid rmod[1:0] is considered valid only when rval is asserted. rmod[1:0] is only used for pos operation and is updated on the rising edge of rfclk. rsx output r29 the pos-phy receive start of transfer (rsx) signal is used to indicate the start of a packet transfer. when rsx is high, the channel number being transferred is given on rdat[31:0]. rsx is only used for pos operation and is updated on the rising edge of rfclk. tfclk input b18 the utopia transmit fifo write clock (tfclk) signal is used to write atm cells to the transmit fifo. tfclk is expected to cycle at a 104 mhz rate. tfclk (continued) input b18 the pos-phy transmit fifo write clock (tfclk) signal is used to write packet data into the 256 byte packet fifo. tfclk is expected to cycle at a 104 mhz rate.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 33 pin name type pin no. function the utopia transmit cell data (tdat[31:0]) bus carries the atm cell octets that are written to the transmit fifo. tdat[31:0] is considered valid only when tenb is simultaneously asserted. tdat[31:0] is sampled on the rising edge of tfclk. tdat[31] tdat[30] tdat[29] tdat[28] tdat[27] tdat[26] tdat[25] tdat[24] tdat[23] tdat[22] tdat[21] tdat[20] tdat[19] tdat[18] tdat[17] tdat[16] tdat[15] tdat[14] tdat[13] tdat[12] tdat[11] tdat[10] tdat[9] tdat[8] tdat[7] tdat[6] tdat[5] tdat[4] tdat[3] tdat[2] tdat[1] tdat[0] input b5 d7 a5 b6 c7 d8 a6 b7 d9 a7 b8 c9 a8 b9 c10 d11 b10 c11 d12 a10 c12 a11 d13 b12 c13 a12 b13 d14 c14 b14 a14 c15 the pos-phy transmit packet data (tdat[31:0]) bus carries the pos packet octets that are written to the transmit fifo. tdat[31:0] bus is considered valid only when tenb is simultaneously asserted. tdat[31:0] is sampled on the rising edge of tfclk. tprty input b15 the utopia transmit bus parity (tprty) signal indicates the parity on the tdat[31:0] bus. a parity error is indicated by a status bit and a maskable interrupt. cells with parity errors are still inserted in the transmit stream, so the tprty input may be unused. odd or even parity may be selected. tprty is considered valid only when tenb is simultaneously asserted. tprty is sampled on the rising edge of tfclk.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 34 pin name type pin no. function tprty (continued) input b15 the pos-phy transmit bus parity (tprty) signal indicates the parity on the tdat[31:0] bus. a parity error is indicated by a status bit and a maskable interrupt. packets with parity errors are still inserted in the transmit stream, so the tprty input may be unused. odd or even parity may be selected. tprty is considered valid only when tenb is simultaneously asserted. tprty is sampled on the rising edge of tfclk. the utopia transmit start of cell (tsoc) signal marks the start of a cell structure on the tdat[31:0] bus. the first word of the cell structure is present on the tdat[31:0] bus when tsoc is high. tsoc must be present for each cell. tsoc is considered valid only when tenb is simultaneously asserted. tsoc is sampled on the rising edge of tfclk. tsoc tsop input d16 the pos-phy transmit start of packet (tsop) signal indicates the start of a packet on the tdat[31:0] bus. tsop is required to be present at all instances for proper operation. tsop must be set high for the first word of a packet on tdat[31:0]. tsop is considered valid only when tenb is simultaneously asserted. tsop is sampled on the rising edge of tfclk. tenb input a19 the utopia transmit write enable (tenb) signal is an active low input which is used to initiate writes to the transmit fifo. when tenb is sampled high, the information sampled on the tdat[31:0], tprty and tsoc signals are invalid. when tenb is sampled low, the information sampled on the tdat[31:0], tprty and tsoc signals are valid and are written into the transmit fifo. tenb is sampled on the rising edge of tfclk.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 35 pin name type pin no. function tenb the pos-phy transmit write enable (tenb) signal is an active low input which is used to initiate writes to the transmit fifo?s. when tenb is sampled high, the information sampled on the tdat[31:0], tprty, tsop, teop, tmod[1:0], and terr signals are invalid. when tenb is sampled low, the information sampled on the tdat[31:0], tprty, tsop, teop, tmod[1:0], and terr signals are valid and are written into the transmit fifo. tenb is sampled on the rising edge of tfclk. tca output d17 the utopia transmit cell available (tca) signal provides direct status indication of when cell space is available in the transmit fifo. when set high, tca indicates that the corresponding transmit fifo is not full and a complete cell may be written. tca is set low to either indicate that the transmit fifo is near full or that the transmit fifo is full. to reduce fifo latency, the fifo depth at which tca indicates "full" can be configured. note that regardless of what fill level tca is set to indicate "full" at, the transmit cell processors still have the full capacity of its fifo to store cells. tca will transition low one tfclk cycle after the payload word 7 or 11 (depending of the configuration) is sampled on the tdat[31:0] bus. tca is updated on the rising edge of tfclk.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 36 pin name type pin no. function dtpa output d17 the pos-phy direct transmit packet available (dtpa) signal provides status indication on the fill status of the transmit fifo. note that regardless of what fill level dtpa is set to indicate "full" at, the transmit packet processors still have the full capacity of its fifo to store cells. when dtpa transitions high, it indicates that the transmit fifo has enough room to store a configurable number of data bytes. when dtpa transitions low, it indicates that the transmit fifo is either full or near full as configured. dtpa is updated on the rising edge of tfclk. teop input b16 the pos-phy transmit end of packet (teop) signal marks the end of packet on the tdat[31:0] bus when configured for packet data. the teop signal marks the last word of a packet on the tdat[31:0] bus. the tmod[1:0] signal indicates how many bytes are in the last word. it is legal to set tsop high at the same time as teop high in order to support one, two, three, or four byte packets. teop is only valid when tenb is simultaneously asserted. teop is only used for pos operation and is sampled on the rising edge of tfclk. terr input a17 the pos-phy transmit error (terr) signal is used to indicate that the current packet must be aborted. packets marked with terr will have the abort sequence appended when transmitted. terr should only be asserted during the last word of the packet being transferred on tdat[31:0]. terr is only considered valid when tenb and teop are simultaneously asserted. terr is ignored for the utopia mode of operation and is sampled on the rising edge of tfclk.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 37 pin name type pin no. function tmod[1:0] input b17 a18 the pos-phy transmit word modulo (tmod[1:0]) bus indicates the size of the current word when configured for packet mode. during a packet transfer, every word on tdat[31:0] must contain four valid bytes of packet data except at the end of the packet where the word is composed of 1, 2, 3, or 4 valid bytes. the number of valid bytes in this last word is specified by tmod[1:0] tmod[1:0] = ?00? tdat[31:0] valid tmod[1:0] = ?01? tdat[31:8] valid tmod[1:0] = ?10? tdat[31:16] valid tmod[1:0] = ?11? tdat[31:24] valid tmod[1:0] is considered valid only when tenb is simultaneously asserted. tmod[1:0] is only used for pos operation and is sampled on the rising edge of tfclk. 9.6 aps serial data interface (20) pin name type pin no. function apsi+[4] apsi-[4] apsi+[3] apsi-[3] apsi+[2] apsi-[2] apsi+[1] apsi-[1] analog lvds input y4 y3 y2 y2 aa3 aa2 ab4 ab3 the differential apsi input (apsi+/-[4:1]) serial data links carries sonet/sdh oc-48 frame data from a mate in bit serial format. each differential pair carries a constituent oc-12 of the data stream. data on apsi+/-[4:1] is encoded in an 8b/10b format extended from ieee std. 802.3. the 8b/10b character bit ?a? is transmitted first and the bit ?j? is transmitted last. when in working mode as set using the apsmode input and the mode[1:0] register bits in the s/uni-2488 master reset, configuration and loopback register, the apsi+/-[4:1] signals carry the receive data from the protect mate. when in protect mode, the apsi+/-[4:1] signals carry the transmit data from the working mate. the four differential pairs in apsi+/-[4:1] are frequency locked but not phase locked. apsi+/-[4:1] are nominally 777.6 mbps data streams.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 38 pin name type pin no. function apsifp input p2 the aps input frame pulse signal (apsifp) provides system timing of the aps input serial interface. apsifp is set high once every 9720 apsifpclk cycles, or multiple thereof, to indicate that the j0 frame boundary 8b/10b character has been delivered on the differential lvds bus (apsi+/-[4:1]). apsifp is sampled on the rising edge of apsifpclk+/-. apso+[4] apso-[4] apso+[3] apso-[3] apso+[2] apso-[2] apso+[1] apso-[1] analog lvds output u1 u2 v3 v4 v1 v2 w2 w3 the differential aps output (apso+/-[4:1]) serial data links carries sonet/sdh oc-48 frame data to a mate in bit serial format. each differential pair carries a constituent oc-12 of the data stream. data on apso+/-[4:1] is encoded in an 8b/10b format extended from ieee std. 802.3. the 8b/10b character bit ?a? is received first and the bit ?j? is received last. when in working mode as set using the apsmode input, the apso+/-[4:1] signals carry the transmit data to the protect mate. when in protect mode, the apso+/-[4:1] signals carry the receive data to the working mate. the four differential pairs in apso+/-[4:1] are frequency locked but not phase locked. apso+/-[4:1] are nominally 777.6 mbps data streams. apsofp output p1 the aps output frame pulse signal (apsofp) provides system timing of the aps output serial interface. apsofp is set high once every 9720 apsifpclk cycles, or multiple thereof, to indicate that the j0 frame boundary 8b/10b character has been delivered on the differential lvds bus (apso+/-[4:1]). apsofp is updated on the rising edge of apsifpclk +/-. apsifpclk input p3 the aps input frame pulse clock (apsifpclk) provides a jitter-free reference clock with which the aps input frame pulse (apsifp) is sampled. also, the 777.76 mhz clock synthesis unit of the aps port uses this clock as its reference. apsifpclk is expected to cycle at a 77.76 mhz rate, and must be a derivative of refclk+/- to ensure that apsifpclk is an exact divide-by-two in frequency compared to refclk+/-.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 39 9.7 microprocessor interface signals (37) pin name type pin no. function csb input f4 the active low chip select (csb) signal is low during s/uni- 2488 register accesses. note that when not being used, csb must be tied low. if csb is not required (i.e. register accesses controlled using the rdb and wrb signals only), csb must be connected to an inverted version of the rstb input. rdb input d2 the active low read enable (rdb) signal is low during a s/uni-2488 read access. the s/uni-2488 drives the d[15:0] bus with the contents of the addressed register while rdb and csb are low. wrb input c1 the active low write strobe (wrb) signal is low during a s/uni-2488 register write access. the d[15:0] bus contents are clocked into the addressed register on the rising wrb edge while csb is low. d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] i/o n1 p4 n2 m1 m2 n4 l1 m3 l2 k1 m4 k2 j1 k3 j2 h1 the bi-directional data bus , d[15:0], is used during s/uni-2488 read and write accesses. a[13]/trs input d28 the test register select signal (trs) selects between normal and test mode register accesses. trs is high during test mode register accesses, and is low during normal mode register accesses. trs may be tied low.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 40 pin name type pin no. function a[12] a[11] a[10] a[9] a[8] a[7] a[6] a[5] a[4] a[3] a[2] a[1] a[0] input j3 h2 j4 h3 g2 f1 h4 g3 f2 e1 g4 e2 d1 the address bus (a[12:0]) selects specific registers during s/uni-2488 register accesses. rstb schmidt ttl input e4 the active low reset (rstb) signal provides an asynchronous s/uni-2488 reset. rstb is a schmidt triggered input with an integral pull-up resistor. ale input e3 the address latch enable (ale) is an active-high signal and latches the address bus a[13:0] when low. when ale is high, the internal address latches are transparent. it allows the s/uni-2488 to interface to a multiplexed address/data bus. the ale input has an integral pull up resistor. intb od output d3 the active low interrupt (intb) is set low when a s/uni-2488 enabled interrupt source is active. the s/uni-2488 may be enabled to report many alarms or events via interrupts. intb is tri-stated when the interrupt is acknowledged via the appropriate register access. intb is an open drain output. 9.8 jtag test access port (tap) signals (5) pin name type pin no. function tck input c30 the test clock (tck) signal provides timing for test operations that can be carried out using the ieee p1149.1 test access port. tms input e27 the test mode select (tms) signal controls the test operations that can be carried out using the ieee p1149.1 test access port. tms is sampled on the rising edge of tck. tms has an integral pull up resistor.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 41 pin name type pin no. function tdi input f27 when the s/uni-2488 is configured for jtag operation, the test data input (tdi) signal carries test data into the s/uni-2488 via the ieee p1149.1 test access port. tdi is sampled on the rising edge of tck. tdi has an integral pull up resistor. tdo tristate output d18 the test data output (tdo) signal carries test data out of the s/uni-2488 via the ieee p1149.1 test access port. tdo is updated on the falling edge of tck. tdo is a tri-state output which is inactive except when scanning of data is in progress. trstb schmidt ttl input d28 the active low test reset (trstb) signal provides an asynchronous s/uni-2488 test access port reset via the ieee p1149.1 test access port. trstb is a schmidt triggered input with an integral pull up resistor. in the event that trstb is not used, it must be connected to rstb. 9.9 analog miscellaneous signals (10) pin name type pin no. function atp[3] atp[2] atp[1] atp[0] analog aj18 ak18 ag2 af3 four analog test ports (atp[0], atp[1], atp[2], atp[3]) are provided for production testing only. these pins must be tied to analog ground (avs) during normal operation. atp[1] and atp[0] are the test ports for the 2488 mbps analog circuitry, while atp[3] and atp[2] are the test ports for the 777.76 mhz lvds analog circuitry. c0 c1 analog ah18 ag18 the analog c0 and c1 pins are provided for applications that must meet sonet/sdh jitter tolerance specifications. a 47nf non-polarized capacitor is attached across c0 and c1 for these applications. when the capacitor is used, the rtype bit in the crsi must be set to logic one for proper operation. when the capacitance is not used, these pins are left floating and the rype register must be set to logic zero for proper operation. c2 c3 analog aj20 ak20 the analog c2 and c3 pins are provided for applications that must meet sonet/sdh jitter transfer specifications. a 4.7nf non-polarized capacitor is attached across c2 and c3 for these applications. when the capacitance is not used, these pins are left floating.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 42 pin name type pin no. function res resk analog ae4 ag1 reference resistor connection. an off-chip 4.75k ? 1% resistor is connected between the positive resistor reference pin res and a kelvin ground contact resk for the aps port lvds reference. an on-chip negative feedback path will force the 1.20v vref voltage onto res, therefore forcing 252a of current to flow through the resistor. resk is electrically connected to avss within the block, but should not be connected to avss, either on-chip or off-chip. 9.10 analog power and ground (107) pin name pin type pin no. function avdh (24) analog power ah20 ah17 ah14 ah10 ah9 ag9 aj9 aj10 aj14 aj17 aj19 ak19 ag20 ag8 the analog power (avdh) pins for the analog core. the avdh pins should be connected through passive filtering networks to a well-decoupled +3.3v analog power supply. please see the operation section for detailed information.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 43 pin name pin type pin no. function avdl(17) analog power ag5 ag6 ag7 ah5 ah6 ah7 aj5 aj6 aj7 ak5 ak6 ak7 ag21 ah21 aj21 ak21 the analog power (avdl) pins for the analog core. the avdl pins should be connected through passive filtering networks to a well-decoupled +1.8v analog power supply. please see the operation section for detailed information.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 44 9.11 digital power and ground pin name pin type pin no. function vdddc digital core power d29 g29 k29 n29 u29 w30 aa28 ah26 ag24 t2 r4 n3 l3 g1 f3 c6 c8 a9 b11 a13 c16 c17 c18 a21 d21 b29 c28 d27 d10 d15 d20 the digital core power (vdddc) pins should be connected to a well-decoupled +1.8v digital power supply.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 45 pin name pin type pin no. function vdddc (cont.) digital core power l4 t4 b2 c3 d4 ag27 ah28 aj29 k27 r27 y27 the digital core power (vdddc) pins should be connected to a well-decoupled +1.8v digital power supply.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 46 pin name pin type pin no. function vss (52) digital ground a1 b1 c2 r1 t1 w1 aa1 ac1 ac2 ac3 ad1 ad2 ae1 ah1 ak1 aj2 ak2 ak14 ag15 ah15 aj15 ag16 ah16 aj16 ak17 ak22 ak23 aj28 ak29 b28 a16 a15 b3 a2 the digital ground (vss) pins should be connected to the digital ground of the digital power supply.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 47 pin name pin type pin no. function vss (52) (continued) digital ground ah3 aj3 ak3 ag4 ah4 aj4 ak4 aj8 ak8 ag11 ah11 aj11 ak11 ag12 ah12 aj12 ag13 ah13 aj13 ak30 aj30 ah29 t30 r30 c29 b30 a30 a29 the digital ground (vss) pins should be connected to the digital ground of the digital power supply.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 48 notes on pin description: 1. all s/uni-2488 inputs and bidirectionals present minimum capacitive loading and operate at cmos/ttl logic levels except: the refclk+/-, rxd+/-, txd+/-, apsi+/-[4:1], apso+/-[4:1] pins which operate at pseudo-ecl (pecl) logic levels. 2. the s/uni-2488 digital outputs and bidirectionals which have 2 ma drive capability are: tbd the s/uni-2488 digital outputs and bidirectionals which have 4 ma drive capability are: tbd the s/uni-2488 digital outputs and bidirectionals which have 6 ma drive capability are: tbd 3. the s/uni-2488 digital outputs are 3.3v tolerant. 4. inputs ale, rstb, tms, tdi and trstb have internal pull-up resistors. 5. the single ended pseudo-ecl inputs and outputs should be terminated in a passive network and interface at pecl levels as described in the operations section. 6. it is mandatory that every digital ground pin (vss) be connected to the printed circuit board ground plane to ensure reliable device operation. 7. it is mandatory that every digital power pin (vdd) be connected to the printed circuit board power plane to ensure reliable device operation. 8. all analog power and ground pins can be sensitive to noise. they must be isolated from the digital power and ground. care must be taken to correctly decouple these pins. please refer to the operations sections. 9. due to esd protection structures in the pads it is necessary to exercise caution when powering a device up or down. esd protection devices behave as diodes between power supply pins and from i/o pins to power supply pins. under extreme conditions it is possible to damage these esd protection devices or trigger latch up. please adhere to the recommended power supply sequencing as described in the operation section of this document. 10. do not exceed 100 ma of current on any pin during the power-up or power-down sequence. refer to the power sequencing description in the operations section. 11. before any input activity occurs, ensure that the device power supplies are within their nominal voltage range. 12. hold the device in the reset condition until the device power supplies are within their nominal voltage range.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 49 13. ensure that all digital power is applied simultaneously, and applied before or simultaneously with the analog power. refer to the power sequencing description in the operations section.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 50 10 functional description 10.1 receive line interface the receive line interface allows direct interface of the s/uni-2488 to optical modules (odls) or other medium interfaces. this block performs clock and data recovery on the incoming 2488.32 mbit/s data stream and sonet a1/a2 pattern framing. the clock recovery unit recovers the clock from the incoming bit serial data stream and is compliant with sonet and sdh jitter tolerance requirements. the clock recovery unit utilizes a low frequency reference clock to train and monitor its clock recovery pll. under loss of signal conditions, the clock recovery unit continues to output a line rate clock that is locked to this reference for keep alive purposes. the clock recovery unit utilizes a 155.52 mhz reference clock. the clock recovery unit provides status bits that indicate whether it is locked to data or the reference and also supports diagnostic loopback and a loss of signal input that squelches normal input data. initially upon start-up, the pll locks to the reference clock, refclk. when the frequency of the recovered clock is within tbd ppm of the reference clock, the pll attempts to lock to the data. once in data lock, the pll reverts to the reference clock if no data transitions occur in tbd bit periods or if the recovered clock drifts beyond tbd ppm of the reference clock. when the transmit clock is derived from the recovered clock (loop timing), the accuracy of the transmit clock is directly related to the refclk reference accuracy in the case of a loss of signal condition. to meet the bellcore gr-253-core sonet network element free-run accuracy specification, the reference must be within +/- tbd ppm. when not loop timed, the refclk accuracy may be relaxed to +/- tbd ppm. the loop filter transfer function is optimized to enable the pll to track the jitter, yet tolerate the minimum transition density expected in a received sonet data signal. the total loop dynamics of the clock recovery pll yield a jitter tolerance that exceeds the minimum tolerance specified for sonet equipment by gr-253-core. please refer to the figure below. figure 7: typical sts-48c (stm-16c) jitter tolerance tbd the serial to parallel converter converts the received bit serial stream to a 16 bit word serial stream.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 51 10.2 sonet/sdh receive line interface (srli) the sonet/sdh receive line interface block performs byte and frame alignment on the incoming 2488 mbit/s data stream based on the sonet/sdh a1/a2 framing pattern. while out of frame, the srli monitors the receive data stream for an occurrence of the a1/a2 framing pattern. the srli adjusts its byte and frame alignment when three consecutive a1 bytes followed by three consecutive a2 bytes occur in the data stream. the srli informs the rrmp framer block when the framing pattern has been detected to reinitialize to the new transport frame alignment. while in frame, the srli maintains the same byte and frame alignment until the rrmp declares out of frame. 10.3 receive regenerator and multiplexor processor (rrmp) the receive regenerator and multiplexor processor (rrmp) block extracts and process the transport overhead of the received data stream. the rrmp frames to the data stream by operating with an upstream pattern detector (srli) that searches for occurrences of the a1/a2 framing pattern. once the srli has found an a1/a2 framing pattern, the rrmp monitors for the next occurrence of the framing pattern 125s later. two framing pattern algorithms are provided to improve performance in the presence of bit errors. in algorithm 1, the rrmp declares frame alignment (removes oof defect) when the 12 a1 and the 12 a2 bytes are seen error-free in the first sts-12 (stm-4) of the sts-48c (stm-16-16c) stream. in algorithm 2, the rrmp declares frame alignment (removes oof defect) when only the last a1 byte and the first four bits of the first a2 byte are seen error-free in the first sts-12 (stm-4) of the sts-48c (stm-16c) . once in frame, the rrmp monitors the framing pattern and declares oof when one or more bit errors in the framing pattern are detected for four consecutive frames. again, depending upon the algorithm either 24 framing bytes or 12 framing bits are examined for bit errors in the framing pattern. the performance of these framing algorithms in the presence of bit errors and random data is robust. when looking for frame alignment the performance of each algorithm is dominated by the alignment algorithm used in the srli which always examines 3 a1 and 3 a2 framing bytes. the probability of falsely framing to random data is less than 0.00001% for either algorithm. once in frame alignment, the rrmp continuously monitors the framing pattern. when the incoming stream contains a 10 -3 ber, the first algorithm provides a 99.75% probability that the mean time between oof occurrences is 1.3 seconds and the second algorithm provides a 99.75% probability that the mean time between oof occurrences is 7 minutes. the rrmp also detects loss of frame (lof) defect and loss of signal (los) defect. lof is declared when an out of frame (oof) condition exists for a total period of 3ms during which there is no continuous in frame period of 3 ms. lof output is removed when an in frame condition exists for a continuous period of 3 ms. los is declared when a continuous period of 20 s without transitions on the received data stream is detected. los is removed when two consecutive framing patterns are found (based on algorithm 1 or algorithm 2) and during the
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 52 intervening time (one frame) there are no continuous periods of 20 s without transitions on the received data stream. the rrmp calculates the section bip-8 error detection code on the scrambled data of the complete frame. the section bip-8 code is based on a bit interleaved parity calculation using even parity. the calculated bip-8 code is compared with the bip-8 code extracted from the b1 byte of sts-1 (stm-0) #1 of the following frame after de-scrambling. any difference indicates a section bip-8 error. the rrmp accumulates section bip-8 errors in a microprocessor readable 16-bit saturating counter (up to 1 second accumulation time). optionally, block section bip-8 errors can be accumulated. the rrmp optionally de-scrambles the received data stream. the rrmp calculates the line bip-8 error detection codes on the de-scrambled line overhead and synchronous payload envelope bytes of the constituent sts-1 (stm-0). the line bip-8 code is based on a bit interleaved parity calculation using even parity. the calculated bip-8 codes are compared with the bip-8 codes extracted from the b2 byte of the constituent sts-1 (stm-0) of the following frame after de-scrambling. any difference indicates a line bip-8 error. the rrmp accumulates line bip-8 errors in a microprocessor readable 24 bits saturating counter (up to 1 second accumulation time). optionally, block bip errors can be accumulated. the rrmp extracts the line remote error indication (rei-l) errors from the m1 byte of sts-1 (stm-0) #3 and accumulates them in a microprocessor readable 24 bits saturating counter (up to 1 second accumulation time). optionally, block line rei errors can be accumulated. the rrmp extracts and filters the k1/k2 aps bytes for three frames. the filtered k1/k2 aps bytes are accessible through microprocessor readable registers. the rrmp also monitors the unfiltered k1/k2 aps bytes to detect aps byte failure (apsbf-l) defect, line alarm indication signal (ais-l) defect and line remote defect indication (rdi-l) defect. aps byte failure is declared when twelve consecutive frames have been received where no three consecutive frames contain identical k1 bytes. the aps byte failure is removed upon detection of three consecutive frames containing identical k1 bytes. the detection of invalid aps codes must be done in software by polling the k1/k2 aps register. line ais is declared when the bit pattern 111 is observed in bits 6, 7, and 8 of the k2 byte for three or five consecutive frames. line ais is removed when any pattern other than 111 is observed for three or five consecutive frames. line rdi is declared when the bit pattern 110 is observed in bits 6, 7, and 8 of the k2 byte for three or five consecutive frames. line rdi is removed when any pattern other than 110 is observed for three or five consecutive frames. the rrmp extracts and filters the synchronization status message (ssm) for eight frames. the filtered ssm is accessible through microprocessor readable registers. rrmp optionally inserts line alarm indication signal (ais-l). the rrmp extracts and serially outputs all the transport overhead (toh) bytes on the rtoh output. the toh bytes are output in the same order that they are received (a1, a2, j0/z0, b1,
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 53 e1, f1, d1-d3, h1-h3, b2, k1, k2, d4-d12, s1/z1, z2/m1/z2 and e2). rtohclk is the generated output clock used to provide timing for the rtoh output. rtohclk is a nominal 20.736 mhz clock generated by gapping a 25.92 mhz clock. sampling rtohfp high with the rising edge of rtohclk identifies the msb of the first a1 byte. figure 8: sts-48c (stm-16-16c) on rtoh a 1 b1 d1 d4 d7 d10 s1 h1 b2 a 2 a 2 a 2 e1 d2 h2 k1 d5 d8 d11 z2 z2 z2 j0 f1 d3 h3 h3 h2 h2 k2 e2 d12 d9 d6 z0 h3 z0 h3 z0 h3 ... a 2 m1 h2 a 2 h2 z2 st s- 1/ st m- 0 #1 2 st s- 1/ st m- 0 #4 st s- 1/ st m- 0 #3 st s- 1/ st m- 0 #2 st s- 1/ st m- 0 #1 st s- 1/ st m- 0 #1 2 st s- 1/ st m- 0 #4 st s- 1/ st m- 0 #3 st s- 1/ st m- 0 #2 st s- 1/ st m- 0 #1 z1 z1 z1 h1 b2 h1 b2 h1 b2 a 1 a 1 a 1 st s- 1/ st m- 0 #1 2 st s- 1/ st m- 0 #4 st s- 1/ st m- 0 #3 st s- 1/ st m- 0 #2 st s- 1/ st m- 0 #1 a 1 b2 z1 h1 first order of transmission ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... z1 h1 b2 a 1 st s- 1/ st m- 0 #5 a 2 h2 z2 st s- 1/ st m- 0 #5 h3 st s- 1/ st m- 0 #5 unused bytes national bytes z0 ... z0 ... z0 z0 or national bytes se co nd or de r of tra ns mi ssi on a maskable interrupt is activated to indicate any change in the status of out of frame (oof), loss of frame (lof), loss of signal (los), line remote defect indication (rdi-l), line alarm indication signal (ais-l), synchronization status message (cossm), aps bytes (coaps) and aps byte failure (apsbf) or any errors in section bip-8, line bip-8 and line remote error indication (rei-l). the rrmp block provides de-scrambled data and frame alignment indication signals for use by the rhpp. 10.4 receive tail trace processor (rttp) the receive tail trace processor (rttp) block monitors the tail trace messages of the receive data stream for trace identifier unstable (tiu) defect and trace identifier mismatch (tim) defect. three tail trace algorithms are defined. the first algorithm is bellcore compliant. the algorithm detects trace identifier mismatch (tim) defect on a 16 or 64 byte tail trace message. a tim defect is declared when none of the last 20 messages matches the expected message. a tim defect is removed when 16 of the last 20 messages match the expected message. the expected tail trace message is a static message written in the expected page of the rttp by an external microprocessor. optionally, the expected message is matched when the tail trace message is all zeros.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 54 the second algorithm is itu compliant. the algorithm detects trace identifier unstable (tiu) defect and trace identifier mismatch (tim) defect on a 16 or 64 byte tail trace message. the current tail trace message is stored in the captured page of the rttp. if the length of the message is 16 bytes, the rttp synchronizes on the msb of the message. the byte with the msb set high is placed in the first location of the captured page. if the length of the message is 64 bytes, the rttp synchronizes on the cr/lf (cr = 0dh, lf = 0ah) characters of the message. the following byte is placed in the first location of the captured page. a persistent tail trace message is declared when an identical message is receive for 3 or 5 consecutive multi-frames (16 or 64 frames). a persistent message becomes the accepted message. the accepted message is stored in the accepted page of the rttp. a tiu defect is declared when one or more erroneous bytes are detected in a total of 8 messages without any persistent message in between. a tiu defect is removed when a persistent message is received. a tim defect is declared when the accepted message does not match the expected message. a tim defect is removed when the accepted message matches the expected message. the expected message is a static message written in the expected page of the rttp by an external microprocessor. optionally, the algorithm declares a match tail trace message when the accepted message is all zeros. the third algorithm is not bellcore/itu compliant. the algorithm detects trace identifier unstable (tiu) on a single continuous tail trace byte. a tiu defect is declared when one or more erroneous bytes are detected in three consecutive 16 byte windows. the first window starts on the first erroneous byte. a tiu defect is removed when an identical byte is received for 48 consecutive frames. a maskable interrupt is activated to indicate any change in the status of trace identifier unstable (tiu) and trace identifier mismatch (tim). 10.5 receive high order path processor (rhpp) the receive high order path processor (rhpp) provides pointer interpretation, extraction of path overhead, extraction of the synchronous payload envelope (virtual container), and path level alarm and performance monitoring. 10.5.1 pointer interpreter the pointer interpreter extracts and validates the h1 and h2 bytes in order to identify the location of the path overhead byte (j1) and the synchronous payload envelop bytes (spe) of the constituent sts-48c (vc-16-16c) payloads. the pointer interpreter is a time multiplexed finite state machine that can process the sts-48c (au-16-16c) pointer. within the pointer interpretation algorithm three states are defined as shown below: norm_state (norm) ais_state (ais)
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 55 lop_state (lop) the transition between states will be consecutive events (indications), e.g., three consecutive ais indications to go from the norm_state to the ais_state. the kind and number of consecutive indications activating a transition is chosen such that the behavior is stable and insensitive to low ber. the only transition on a single event is the one from the ais_state to the norm_state after receiving a ndf enabled with a valid pointer value. it should be noted that, since the algorithm only contains transitions based on consecutive indications, this implies that, for example, non- consecutively received invalid indications do not activate the transitions to the lop_state. figure 9: pointer interpretation state diagram norm lop ais 8 x inv_point 3 x ais_ind 3 x eq_new_point ndf_enable 3 x ais_ind 8 x inv_point 8 x ndf_enable 3 x eq_new_point 3 x eq_new_point ndf_enable inc_ind/dec_ind the following events (indications) are defined: norm_point: disabled ndf + ss + offset value equal to active offset. ndf_enable: enabled ndf + ss + offset value in range of 0 to 782. ais_ind: h1 = ffh + h2 = ffh.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 56 inc_ind: disabled ndf + ss + majority of i bits inverted + no majority of d bits inverted + previous ndf_enable, inc_ind or dec_ind more than 3 frames ago. dec_ind: disabled ndf + ss + majority of d bits inverted + no majority of i bits inverted + previous ndf_enable, inc_ind or dec_ind more than 3 frames ago. inv_point: not any of the above (i.e.: not norm_point, not ndf_enable, not ais_ind, not inc_ind and not dec_ind). new_point: disabled ndf + ss + offset value in range of 0 to 782 but not equal to active offset. note 1: active offset is defined as the accepted current phase of the spe (vc) in the norm_state and is undefined in the other states. note 2: enabled ndf is defined as the following bit patterns: 1001, 0001, 1101, 1011 and 1000. note 3: disabled ndf is defined as the following bit patterns: 0110, 1110, 0010, 0100 and 0111. note 4: the remaining six ndf bit patterns (0000, 0011, 0101, 1010, 1100, 1111) result in an inv_point indication. note 5: ss bits are unspecified in sonet and have bit pattern 10 in sdh. note 6: the use of ss bits in definition of indications may be optionally disabled. note 7: the requirement for previous ndf_enable, inc_ind or dec_ind be more than 3 frames ago may be optionally disabled. note 8: new_point is also an inv_point. note 9: the requirement for the pointer to be within the range of 0 to 782 in 8 x ndf_enable may be optionally disabled. note 10: lop is not declared if all the following conditions exist: - the received pointer is out of range (>782), - the received pointer is static, - the received pointer can be interpreted, according to majority voting on the i and d bits, as a positive or negative justification indication, after making the requested justification, the received pointer continues to be interpretable as a pointer justification.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 57 - when the received pointer returns to an in-range value, the s/uni-2488 will interpret it correctly. note 11: lop will exit at the third frame of a three frame sequence consisting of one frame with ndf enabled followed by two frames with ndf disabled, if all three pointers have the same legal value. the transitions indicated in the state diagram are defined as follows: inc_ind/dec_ind: offset adjustment (increment or decrement indication) 3 x eq_new_point: three consecutive equal new_point indications ndf_enable: single ndf_enable indication 3 x ais_ind: three consecutive ais indications 8 x inv_point: eight consecutive inv_point indications 8 x ndf_enable eight consecutive ndf_enable indications note 1: the transitions from norm_state to norm_state do not represent state changes but imply offset changes. note 2: 3 x eq_new_point takes precedence over other events and may optionally reset the inv_point count. note 3: all three offset values received in 3 x eq_new_point must be identical. note 4: "consecutive event counters" are reset to zero on a change of state (except the inv_point counter). note 5 "consecutive event counters" are reset to zero on a change of state except for consecutive ndf count. lop is declared on entry to the lop_state after eight consecutive invalid pointers or eight consecutive ndf enabled indications pais is declared on entry to the ais_state after three consecutive ais indications
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 58 10.5.2 concatenation pointer interpreter state machine the concatenation pointer interpreter extracts and validates the h1 and h2 concatenation bytes. within the pointer interpretation algorithm three states are defined as shown below. conc_state (conc) aisc_state (aisc) lopc_state (lopc) the transitions between the states will be consecutive events (indications), e.g. three consecutive ais indications to go from the conc_state to the aisc_state. the kind and number of consecutive indications activating a transition is chosen such that the behaviour is stable and insensitive to low ber. figure 10: concatenation pointer interpretation state diagram conc lopc aisc 8 x inv_point 3 x ais_ind 3 x conc_ind 3 x ais_ind 8 x inv_point 3 x conc_ind the following events (indications) are defined: conc_ind: enabled ndf + dd + ? 1111111111? ais_ind: h1 = ffh + h2 = ffh inv_point: not any of the above (i.e.: not conc_ind and not ais_ind)
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 59 note 1: enabled ndf is defined as the following bit patterns: 1001, 0001, 1101, 1011 and 1000. note 2: the remaining eleven ndf bit patterns (0000, 0010, 0011, 0100, 0101, 0110, 0111, 1010, 1100, 1110, 1111) result in an inv_point indication. note 3: dd bits are unspecified in sonet/sdh. the transitions indicated in the state diagram are defined as follows: 3 x conc_ind: three consecutive conc indications 3 x ais_ind: three consecutive ais indications 8 x inv_point: eight consecutive inv_point indications note 1: "consecutive event counters" are reset to zero on a change of state. lopc is declared on entry to the lopc_state after eight consecutive pointers with values other than concatenation indications paisc is declared on entry to the aisc_state after three consecutive ais indications 10.5.3 error monitoring the rhpp calculates the path bip-8 error detection codes on the sonet (sdh) payloads. the path bip-8 code is based on a bit interleaved parity calculation using even parity. the calculated bip-8 codes are compared with the bip-8 codes extracted from the b3 byte of the sts (vc) payload of the following frame. any differences indicate a path bip-8 error. the rhpp accumulates path bip-8 errors in a microprocessor readable 16 bits saturating counter (up to 1 second accumulation time). optionally, block bip-8 errors can be accumulated. the rhpp extracts the path remote error indication (rei-p) errors from bits 1, 2, 3 and 4 of the path status byte (g1) and accumulates them in a microprocessor readable 16 bits saturating counter (up to 1 second accumulation time). optionally, block block rei errors can be accumulated. the rhpp monitors the path signal label byte (c2) payload to validate change in the accepted path signal label (apsl). the same psl byte must be received for three or five consecutive
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 60 frames (selectable by the psl5 bit in the configuration register) before being considered accepted. the rhpp also monitors the path signal label byte (c2) to detect path payload label unstable (plu-p) defect. a psl unstable counter is increment every time the received psl differs from the previously received psl (an erroneous psl will cause the counter to be increment twice, once when the erroneous psl is received and once when the error free psl is received). the psl unstable counter is reset when the same psl value is received for three or five consecutive frames (selectable by the psl5 bit in the configuration register). plu-p is declared when the psl unstable counter reaches five. plu-p is removed when the psl unstable counter is reset. the rhpp also monitors the path signal label byte (c2) to detect path payload label mismatch (plm-p) defect. plm-p is declared when the accepted psl does not match the expected psl according to table 1. plm-p is removed when the accepted psl match the expected psl according to table 1. the accepted psl is the same psl value received for three or five consecutive frames (selectable by the psl5 bit in the configuration register). the expected psl is a programmable psl value. the rhpp also monitors the path signal label byte (c2) to detect path unequipped (uneq-p) defect. uneq-p is declared when the accepted psl is 00h and the expected psl is not 00h. uneq-p is removed when the accepted psl is not 00h or when the accepted psl is 00h and the expected psl is 00h. the accepted psl is the same psl value received for three or five consecutive frames (selectable by the psl5 bit in the configuration register). the expected psl is a register programmable psl value. the rhpp also monitors the path signal label byte (c2) to detect path payload defect indication (pdi-p) defect. pdi-p is declared when the accepted psl is a pdi defect that matches the expected pdi defect. the pdi-p defect is removed when the accepted psl is not a pdi defect or when the accepted psl is a pdi defect that does not match the expected pdi defect. the accepted psl is the same psl value received for three or five consecutive frames (selectable by the psl5 bit in the configuration register). table 2 gives the expected pdi defect based on the programmable pdi and pdi range register values. table 1: plm-p, uneq-p and pdi-p defects declaration expected psl accepted psl plm-p uneq-p pdi-p 00 unequipped match inactive inactive 01 equipped non specific mismatch inactive inactive 02-e0 fd-ff equipped specific mismatch inactive inactive = exp pdi match inactive active 00 unequipped e1-fc pdi != exp pdi mismatch inactive inactive 01 equipped non specific 00 unequipped mismatch active inactive
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 61 01 equipped non specific match inactive inactive 02-e0 fd-ff equipped specific match inactive inactive = exp pdi match inactive active e1-fc pdi != exp pdi mismatch inactive inactive 00 unequipped mismatch active inactive 01 equipped non specific match inactive inactive = exp psl match inactive inactive 02-e0 fd-ff equipped specific != exp psl mismatch inactive inactive = exp pdi match inactive active 02-ff equipped specific pdi e1-fc pdi != exp pdi mismatch inactive inactive table 2: expected pdi defect based on pdi and pdi range values pdi register value pdi range register value exp pdi pdi register value pdi range register value exp pdi disable disable ef 00000 enable none 01111 enable e1-ef disable e1 disable f0 00001 enable e1-e1 10000 enable e1-f0 disable e2 disable f1 00010 enable e1-e2 10001 enable e1-f1 disable e3 disable f2 00011 enable e1-e3 10010 enable e1-f2 disable e4 disable f3 00100 enable e1-e4 10011 enable e1-f3 disable e5 disable f4 00101 enable e1-e5 10100 enable e1-f4 disable e6 disable f5 00110 enable e1-e6 10101 enable e1-f5 disable e7 disable f6 00111 enable e1-e7 10110 enable e1-f6 disable e8 disable f7 01000 enable e1-e8 10111 enable e1-f7 disable e9 disable f8 01001 enable e1-e9 11000 enable e1-f8 disable ea disable f9 01010 enable e1-ea 11001 enable e1-f9 disable eb disable fa 01011 enable e1-eb 11010 enable e1-fa 01100 disable ec 11011 disable fb
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 62 enable e1-ec enable e1-fb disable ed disable fc 01101 enable e1-ed 11100 enable e1-fc disable ee 01110 enable e1-ee the rhpp monitors bits 5, 6 and 7 of the path status byte (g1) to detect path remote defect indication (rdi-p) and path enhanced remote defect indication (erdi-p) defects. rdi-p is declared when bit 5 of the g1 byte is set high for five or ten consecutive frames (selectable by the prdi10 bit in the configuration register). rdi-p is removed when bit 5 of the g1 byte is set low for five or ten consecutive frames. erdi-p is declared when the same 010, 100, 101, 110 or 111 pattern is detected in bits 5, 6 and 7 of the g1 byte for five or ten consecutive frames (selectable by the prdi10 bit in the configuration register). erdi-p is removed when the same 000, 001 or 011 pattern is detected in bits 5, 6 and 7 of the g1 byte for five or ten consecutive frames. the rhpp extracts and serially outputs all the path overhead (poh) bytes on the time multiplexed rpoh port. the poh bytes are output in the same order that they are received (j1, b3, c2, g1, f2, h4, z3, z4 and n1). rpohclk is the generated output clock used to provide timing for the rpoh port. rpohclk is a nominal 20.736 mhz clock generated by gapping a 25.92 mhz clock. sampling rpohfp high with the rising edge of rpohclk identifies the msb of the first j1 byte. 10.6 sonet/sdh virtual container aligner (svca) the sonet (sdh) virtual container aligner (svca) block aligns the payload data from an incoming sonet (sdh) data stream to a new transport frame reference. the alignment is accomplished by recalculating the sts (au) payload pointer value based on the offset between the transport overhead of the incoming data stream and that of the outgoing data stream. frequency offsets (e.g., due to plesiochronous network boundaries, or the loss of a primary reference timing source) and phase differences (due to normal network operation) between the incoming data stream and the outgoing data stream are accommodated by pointer adjustments in the outgoing data stream. 10.6.1 elastic store the elastic store performs rate adaptation between the line side interface and the system side interface. the entire incoming payload, including path overhead bytes, is written into a first-in- first-out (fifo) buffer at the incoming byte rate. each fifo word stores a payload data byte and a one bit tag labeling the j1 byte. incoming pointer justifications are accommodated by writing into the fifo during the negative stuff opportunity byte or by not writing during the positive stuff
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 63 opportunity byte. data is read out of the fifo in the elastic store block at the outgoing byte rate by the pointer generator. analogously, outgoing pointer justifications are accommodated by reading from the fifo during the negative stuff opportunity byte or by not reading during the positive stuff opportunity byte. the fifo read and write addresses are monitored. pointer justification requests will be made to the pointer generator based on the proximity of the addresses relative to programmable thresholds. the pointer generator schedules a pointer increment event if the fifo depth is below the lower threshold and a pointer decrement event if the depth is above the upper threshold. fifo underflow and overflow events are detected and path ais is optionally inserted in the outgoing data stream for three frames to alert downstream elements of data corruption. 10.6.2 pointer generator the pointer generator generates the h1 and h2 bytes in order to identify the location of the path overhead byte (j1) and all the synchronous payload envelope bytes (spe) of the sts-48c (vc16-16c) payloads. within the pointer generator algorithm, five states are defined as shown below: norm_state (norm) ais_state (ais) ndf_state (ndf) inc_state (inc) dec_state (dec) the transition from the norm to the inc, dec, and ndf states are initiated by events in the elastic store block. the transition to/from the ais state are controlled by the pointer interpreter in the receive high order path processor block. the transitions from inc, dec, and ndf states to the norm state occur autonomously with the generation of special pointer patterns.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 64 figure 11: pointer generation state diagram norm_point pi_ais ais_ind pi_ais pi_norm pi_ais es_uppert dec_ind es_lowert inc_ind pi_ais pi_lop fo_discont ndf_enable norm inc ais ndf dec the following events, indicated in the state diagram, are defined: es_lowert: es filling is below the lower threshold + previous inc_ind, dec_ind or ndf_enable more than three frames ago. es_uppert: es filling is above the upper threshold + previous inc_ind, dec_ind or ndf_enable more than three frames ago.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 65 fo_discont: frame offset discontinuity pi_ais: pi in ais state pi_lop: pi in lop state pi_norm: pi in norm state note 1 a frame offset discontinuity occurs if an incoming ndf enabled is received, or if an es overflow/underflow occurred. the autonomous transitions indicated in the state diagram are defined as follows: inc_ind: transmit the pointer with ndf disabled and inverted i bits, transmit a stuff byte in the byte after h3, increment active offset. dec_ind: transmit the pointer with ndf disabled and inverted d bits, transmit a data byte in the h3 byte, decrement active offset. ndf_enable: accept new offset as active offset, transmit the pointer with ndf enabled and new offset. norm_point: transmit the pointer with ndf disabled and active offset. ais_ind: active offset is undefined, transmit an all-1's pointer and payload. note 1 active offset is defined as the phase of the spe (vc). note 2 the ss bits are undefined in sonet, and has bit pattern 10 in sdh note 3 enabled ndf is defined as the bit pattern 1001. note 4 disabled ndf is defined as the bit pattern 0110. 10.7 receive cell and frame processor (rcfp) the receive cell and frame processor (rcfp) performs both atm and ppp processing. it has the capability to process a single sts-48c (stm-16c) channel.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 66 10.7.1 atm cell delineation cell delineation is the process of framing to atm cell boundaries using the header check sequence (hcs) field found in the cell header. the hcs is a crc-8 calculation over the first 4 octets of the atm cell header. when performing delineation, correct hcs calculations are assumed to indicate cell boundaries. cells are assumed to be byte-aligned to the synchronous payload envelope. the cell delineation algorithm searches the 53 possible cell boundary candidates individually to determine the valid cell boundary location. while searching for the cell boundary location, the cell delineation circuit is in the hunt state. when a correct hcs is found, the cell delineation state machine locks on the particular cell boundary, corresponding to the correct hcs, and enters the presync state. the presync state validates the cell boundary location. if the cell boundary is invalid, an incorrect hcs will be received within the next delta cells, at which time a transition back to the hunt state is executed. if no hcs errors are detected in this presync period, the sync state is entered. while in the sync state, synchronization is maintained until alpha consecutive incorrect hcs patterns are detected. in such an event a transition is made back to the hunt state. the state diagram of the delineation process is shown in below. figure 12: cell delineation state diagram hunt presync sync correct hcs (byte by byte) delta consecutive correct hcs's (cell by cell) incorrect hcs (cell by cell) alpha consecutive incorrect hcs's (cell by cell)
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 67 the values of alpha and delta determine the robustness of the delineation process. alpha determines the robustness against false misalignments due to bit errors. delta determines the robustness against false delineation in the synchronization process. alpha is chosen to be 7 and delta is chosen to be 6. these values result in an average time to delineation of 2 s for the sts-48c (stm-16c) rate. 10.7.2 atm descrambler the self-synchronous descrambler operates on the 48 byte cell payload only. the circuitry descrambles the information field using the x 43 + 1 polynomial. the descrambler is disabled for the duration of the header and hcs fields and may optionally be disabled for the payload. 10.7.3 atm cell filter and hcs verification cells are filtered (or dropped) based on hcs errors and/or a cell header pattern. cell filtering is optional and is enabled through the rcfp registers. cells are passed to the receive fifo while the cell delineation state machine is in the sync state as described above. when both filtering and hcs checking are enabled, cells are dropped if uncorrectable hcs errors are detected, or if the corrected header contents match the pattern contained in the rcfp idle cell header and mask register. idle cell filtering is accomplished by writing the appropriate cell header pattern into the rcfp idle cell header and mask pattern register. idle/unassigned cells are assumed to contain the all zeros pattern in the vci and vpi fields. the rcfp idle cell header and mask register allows filtering control over the contents of the gfc, pti, and clp fields of the header. the hcs is a crc-8 calculation over the first 4 octets of the atm cell header. the rcfp block verifies the received hcs using the polynomial, x 8 + x 2 + x + 1. the coset polynomial, x 6 + x 4 + x 2 + 1, is added (modulo 2) to the received hcs octet before comparison with the calculated result. atm performance monitor the performance monitor consists of two 16-bit saturating hcs error event counters and a 32-bit saturating receive cell counter. the first error counter accumulates uncorrectable hcs errors. a 32-bit receive cell counter counts all cells written into the receive fifo. filtered cells are not counted. each counter may be read through the microprocessor interface. circuitry is provided to latch these counters so that their values can be read while simultaneously resetting the internal counters to 0 or 1, if appropriate, so that a new period of accumulation can begin without loss of any events. it is intended that the counter be polled at least once per second so as not to miss any counted events.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 68 10.7.5 pos overhead removal the overhead removal consists of stripping sonet/sdh overhead bytes from the data stream. once overhead bytes are removed, the data stream consists of ppp/hdlc frame octets that can be fed directly to the descrambler or the ppp/hdlc frame delineation block. 10.7.6 pos descrambler when enabled, the self-synchronous descrambler operates on the ppp frame data, descrambling the data with the polynomial x 43 +1. descrambling is performed on the raw data stream, before any ppp frame delineation or byte destuffing is performed. data scrambling can provide for a more robust system preventing the injection of hostile patterns into the data stream. 10.7.7 pos ppp/hdlc frame delineation the ppp/hdlc frame delineation is performed on the descrambled data and consists of arranging the framed octets. frame boundaries are found by searching for the flag character (0x7e). flags are also used to fill inter-packet spacing. this block removes the flag and idle sequences and passes the data onto the byte destuffing block. the ppp/hdlc frame format is shown in the figure below. figure 13: ppp/hdlc over sonet frame format flag packet (ppp or other) fcs flag flag pos frame in the event of a fifo overflow caused by the fifo being full while a packet is being received, the packet is marked with an error so it can be discarded by the system. subsequent bytes associated with this now aborted frame are discarded. reception of ppp/hdlc data resumes when a start of packet is encountered and the fifo level is below a programmable reception initialization level. 10.7.8 pos byte destuffing the byte destuffing algorithm searches the control escape character (0x7d). these characters, listed in the table below are added for transparency in the transmit direction and must be removed to recover the user data. when the control escape character is encountered, it is removed and the following data byte is xored with 0x20. therefore, any escaped data byte will be processed properly by the s/uni-2488.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 69 table 3: byte destuffing original escaped 7e (flag sequence) 7d-5e 7d (control escape) 7d-5d aborted packet 7d-7e 10.7.9 pos fcs check the fcs generator performs a crc-ccitt or crc-32 calculation on the whole pos frame, after byte destuffing and data descrambling scrambling. a parallel implementation of the crc polynomial is used. the crc algorithm for the frame checking sequence (fcs) field is either a crc-ccitt or crc-32 function. the crc-ccitt is two bytes in size and has a generating polynomial g(x) = 1 + x 5 + x 12 + x 16 . the crc-32 is four bytes in size and has a generating polynomial g(x) = 1 + x + x 2 + x 4 + x 5 + x 7 + x 8 + x 10 + x 11 + x 12 + x 16 + x 22 + x 23 + x 26 + x 32 . the first fcs bit transmitted is the coefficient of the highest term. . packets with fcs errors are marked as such and should be discarded by the system. figure 14: crc decoder + d 0 + d 1 + + g n-1 g 2 g 1 message d n-1 . . . 10.7.10 pos performance monitor the performance monitor consists of four 16-bit saturating error event counters, one 32-bit saturating received good packet counter, and one 40-bit counter for accumulating packet bytes. one of the error event counters accumulates fcs errors. the second error event counter accumulates minimum length violation packets. the third error event counter accumulates maximum length violation packets. the fourth error event counter accumulates aborted packets. the 32-bit receive good packet counter counts all error free packets. each counter may be read through the microprocessor interface. circuitry is provided to latch these counters so that their values can be read while simultaneously resetting the internal counters to 0 or 1, whichever is appropriate, so that a new period of accumulation can begin without loss of any events. the counters should be polled at least once per second so error events will not be missed.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 70 the rcfp monitors the packets for both minimum and maximum length errors. when a packet size is smaller than minpl[7:0], the packet is marked with an error but still written into the fifo. malformed packets, that is packets that do not at least contain four bytes, are discarded and will be counted as a minimum packet size violation. when the packet size exceeds maxpl[16:0] the packet is marked with an error and the bytes beyond the maximum count are discarded. 10.8 receive scalable data queue (rxsdq) the rxsdq provides a fifo to separate the line-side timing from the higher layer atm/pos link layer timing. the rxsdq has two modes of operations, atm and pos. 10.8.1 receive atm fifo the rxsdq is responsible for holding up to 48 cells until they are read by the receive system interface. receive fifo management functions include filling the receive fifo, indicating when cells are available to be read from the receive fifo, maintaining the receive fifo read and write pointers, and detecting fifo overrun conditions. upon detection of an overrun, the fifo discards the current cell and discards the incoming cells until there is room in the fifo. fifo overruns are indicated through a maskable interrupt and register bit and are considered a system error. 10.8.2 receive pos fifo the rxsdq contains 48 sixteen byte blocks for fifo storage, along with management circuitry for reading and writing the fifo. the receive fifo provides for the separation of the physical layer timing from the system timing. receive fifo management functions include filling the receive fifo, indicating when packets or bytes are available to be read from the receive fifo, maintaining the receive fifo read and write pointers, and detecting fifo overrun and underrun conditions. upon detection of an overrun, the fifo aborts the current packet and discards the current incoming bytes until there is room in the fifo. once enough room is available, as defined by the bt[7:0] register bit settings, the rxsdq will wait for the next start of packet before writing any data into the fifo. fifo overruns are indicated through a maskable interrupt and register bit and are considered a system error. a fifo underrun is caused when the system interface tries to read more data words while the fifo is empty. this action will be detected and reported through the fudri interrupt, but it is not considered a system error. the system will continue to operate normally. in that situation, rval can be used by the link layer device to find out if valid or invalid data is provided on the system interface.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 71 10.9 receive phy interface (rxphy) the s/uni-2488 receive system interface can be configured for atm or pos mode. when configured for atm applications, the system interface provides a 32-bit receive utopia level 3 compatible bus to allow the transfer of atm cells between the atm layer device and the s/uni- 2488. when configured for pos applications, the system interface provides either a 32-bit pos- phy level 3 compliant bus for the transfer of atm cells and data packets between the link layer device and the s/uni-2488. the link layer device can implement various protocols, including ppp and hdlc. 10.9.1 receive utopia level 3 interface the utopia level 3 compliant interface accepts a read clock (rfclk) and read enable signal (renb). the interface indicates the start of a cell (rsoc) when data is read from the receive fifo (using the rising edges of rfclk). the rca signal indicates when a cell is available for transfer on the receive data bus rdat[31:0]. the rprty signal reports the parity on the rdat[31:0] bus (selectable as odd or even parity). this interface also indicates fifo overruns via a maskable interrupt and register bits. read accesses while rca is deasserted will output invalid data. 10.9.2 receive pos-phy level 3 the interface accepts a read clock (rfclk) and read enable signal (renb) when data is read from the receive fifo (using the rising edge of the rfclk). the start of packet rsop marks the first byte of receive packet data on the rdat[31:0]. the rprty signal determine the parity on the rdat[31:0] bus (selectable as odd or even parity). the end of a packet is indicated by the reop signal. signal rerr is provided to indicate that an error in the received packet has occurred (the error may have several causes include an abort sequence or an fcs error). the rval signal is used to indicate when rsop, reop, rerr and rdat[31:0] are valid. read accesses while rval is logic 0 are ignored and will output invalid data. rsx indicates the start of a transfer and marks the clock cycle where the in-band channel address is given on the rdat bus. the rxphy performs the polling procedure to select which phy address is serviced. 10.10 transmit line interface the transmit line interface allows the s/uni-2488 to directly interface with optical modules (odls) or other medium interfaces. this block performs clock synthesis and performs parallel to serial conversion of the incoming outgoing 2488.32 mbit/s data stream. the transmit clock is synthesized from a 155.52. mhz reference. the transfer function yields a typical low pass corner of tbd mhz above which reference jitter is attenuated at tbd db per octave. the design of the loop filter and pll is optimized for minimum intrinsic jitter. with a jitter free 155.52mhz reference, the intrinsic jitter is typically less than tbd ui rms when measured using a high pass filter with a tbd cutoff frequency.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 72 the refclk reference should be within 20 ppm to meet the sonet free-run accuracy requirements specified in gr-253-core. the parallel to serial converter (piso) converts the transmit byte serial stream to a bit serial stream. the transmit bit serial stream appears on the txd+/- pecl outputs. 10.11 sonet/sdh transmit line interface (stli) the sonet/sdh transmit line interface block properly formats the outgoing 2488 mbit/s data stream. this block interfaces the trmp to the tx line interface block. 10.12 transmit regenerator multiplexor processor (trmp) the transmit regenerator and multiplexor processor (trmp) block inserts the transport overhead bytes in the transmit data stream. the trmp accumulates the line bip-8 errors detected by the rrmp during the last receive frame. the line bip-8 errors are returned to the far end as line remote error indication (rei-l) during the next transmit frame. because the rrmp and the trmp are in two different clock domains, none, one or two line bip-8 errors can be accumulated per transmit frame. the minimum value between the maximum rei-l and the accumulator count is returned as the line rei-l in the m1 byte of sts-1 (stm-0) #3. optionally, block bip-24 errors can be accumulated. for sts-48c (stm-16c), the maximum single bip-8 error count is 0xff while the maximum block bip-24 error count is 0x10. the trmp serially inputs all the transport overhead (toh) bytes from the ttoh port. the toh bytes must be input in the same order that they are transmitted (a1, a2, j0/z0, b1, e1, f1, d1- d3, h1-h3, b2, k1, k2, d4-d12, s1/z1, z2/m1/z2 and e2). ttohclk is the generated output clock used to provide timing for the ttoh port. ttohclk is a nominal 20.736 mhz clock generated by gapping a 25.92 mhz clock. sampling ttohfp high with the rising edge of ttohclk identifies the msb of the first a1 byte. ttohen port is used to validate the byte insertion on a byte per byte basis. when ttohen is sampled high on the msb of the serial byte, the serial byte is inserted. when ttohen is sampled low on the msb of the serial byte, the serial byte is discarded.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 73 figure 15: sts-48c (stm-16-16c) on ttoh a1 b1 d1 d4 d7 d10 s1 h1 b2 a2 a2 a2 e1 d2 h2 k1 d5 d8 d11 z2 z2 z2 j0 f1 d3 h3 h3 h2 h2 k2 e2 d12 d9 d6 z0 h3 z0 h3 z0 h3 ... a2 m1 h2 a2 h2 z2 sts-1/stm-0 #12 sts-1/stm-0 #4 sts-1/stm-0 #3 sts-1/stm-0 #2 sts-1/stm-0 #1 sts-1/stm-0 #12 sts-1/stm-0 #4 sts-1/stm-0 #3 sts-1/stm-0 #2 sts-1/stm-0 #1 z1 z1 z1 h1 b2 h1 b2 h1 b2 a1 a1 a1 sts-1/stm-0 #12 sts-1/stm-0 #4 sts-1/stm-0 #3 sts-1/stm-0 #2 sts-1/stm-0 #1 a1 b2 z1 h1 first order of transmission ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... z1 h1 b2 a1 sts-1/stm-0 #5 a2 h2 z2 sts-1/stm-0 #5 h3 sts-1/stm-0 #5 unused bytes national bytes z0 ... z0 ... z0 z0 or national bytes second order of transmission note, only the overhead from the first sts-12 (stm-4) of the sts-48c (stm-16c) can be sourced. overhead from the other three sts-12s (stm-4s) are internally generated assigned or are assigned default values as described below. the trmp also inserts most of the transport overhead bytes from internal registers. since there is multiple sources for the same overhead byte, the toh bytes must be prioritised according to table 4 before being inserted into the data stream. table 4: toh insertion priority byte highest priority lowest priority a1 76h (a1err=1) f6h (a1a2en=1) ttoh (ttohen=1) a1 pass through a2 28h (a1a2en=1) ttoh (ttohen=1) a2 pass through j0 sts-1/stm-0 # (j0z0incen=1) j0[7:0] (traceen=1 ) j0v (j0regen=1) ttoh (ttohen=1) j0 pass through z0 sts-1/stm-0 # (j0z0incen=1) z0v (z0regen=1) ttoh (ttohen=1) z0 pass through calculated b1 xor ttoh (ttohen=1 & b1masken=1) b1 ttoh (ttohen=1 & b1masken=0) calculated b1 xor b1mask e1 e1v (e1regen=1) ttoh (ttohen=1) e1 pass through f1 f1v ttoh f1 pass through
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 74 (f1regen=1) (ttohen=1) d1-d3 d1d3v (d1d3regen=1) ttoh (ttohen=1) d1-d3 pass through h1 pass through xor ttoh (ttohen=1 & hmasken=1) h1 ttoh (ttohen=1 & hmasken=0) h1 pass through xor h1mask h2 pass through xor ttoh (ttohen=1 & hmasken=1) h2 ttoh (ttohen=1 & hmasken=0) h2 pass through xor h2mask h3 ttoh (ttohen=1) h3 pass through calculated b2 xor ttoh (ttohen=1 & b2masken=1) b2 ttoh (ttohen=1 & b2masken=0) calculated b2 xor b2mask k1 aps[15:8] (apsen=1) k1v (k1k2regen=1) ttoh (ttohen=1) k1 pass through k2 aps[7:0] (apsen=1) k2v (k1k2regen=1) ttoh (ttohen=1) k2 pass through d4-d12 d4d12v (d4d12regen=1) ttoh (ttohen=1) d4-d12 pass through s1 s1v (s1regen=1) ttoh (ttohen=1) s1 pass through z1 z1v (z1regen=1) ttoh (ttohen=1) z1 pass through z2 z2v (z2regen=1) ttoh (ttohen=1) z2 pass through m1 lrei[7:0] (lreien=1) ttoh (ttohen=1) m1 pass through e2 e2v (e2regen=1) ttoh (ttohen=1) e2 pass through national nationalv (nationalen=1) ttoh (ttohen=1) national pass through unused unusedv (unuseden=1) ttoh (ttohen=1) unused pass through pld pld pass through the z0def register bit defines the z0/national growth bytes for row #1. when z0def is set to logic one, the z0/national bytes are defined according to itu. when z0def is set to logic zero, the z0/national bytes are defined according to bellcore.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 75 table 5: z0/national growth bytes definition for row #1 trmp mode type z0def = 1 z0def = 0 z0 from sts-1/stm-0 #1 to #4 from sts-1/stm-0 #1 to #12 sts-48c (stm-16) slave mode national from sts-1/stm-0 #5 to #12 none the h1, h2, b1 and b2 bytes input from the ttoh port are inserted or are used as a mask to toggle bits in the corresponding h1, h2, b1 and b2 bytes depending on the hmask, b1mask and b2mask register bits of the trmp error insertion register. when the hmask, b1mask or b2mask register bit is set low and ttohen is sampled high on the msb of the serial h1, h2, b1 or b2 byte, the serial byte is inserted in place of the corresponding byte. when the hmask, b1mask or b2mask register bit is set high and ttohen is sampled high on the msb of the serial h1, h2, b1 or b2 byte, the serial byte is xor with the corresponding path payload pointer (already in the data stream) or the calculated bip-8 byte before being inserted. the trmp inserts the aps bytes detected by the rrmp during the last receive frame. the aps bytes are returned to the far end by the trmp during the next transmit frame. because the rrmp and the trmp are in two different clock domains, none, one or two aps bytes can be sampled per transmit frame. the last received aps bytes are transmitted. the trmp inserts the line remote defect indication (rdi-l) into the data stream. when line rdi must be inserted, the 110 pattern is inserted in bits 6, 7 and 8 of the k2 byte of sts-1 (stm-0) #1. line rdi insertion has priority over toh byte insertion. the trmp also inserts the line alarm indication signal (ais-l) into the data stream. when line ais must be inserted, all ones are inserted in the line overhead and in the payload (all bytes of the frame except the section overhead bytes). line ais insertion has priority over line rdi insertion and toh byte insertion. the trmp calculates the line bip-8 error detection codes on the transmit data stream. one line bip-8 error detection code is calculated for each of the constituent sts-1 (stm-0). the line bip- 8 byte is calculated on the unscrambled bytes of the sts-1 (stm-0) except for the 9 soh bytes. the line bip-8 byte is based on a bit interleaved parity calculation using even parity. for each sts-1 (stm-0), the calculated bip-8 error detection code is inserted in the b2 byte of the following frame before scrambling. the trmp optionally scrambles the transmit data stream. the trmp calculates the section bip-8 error detection code on the transmit data stream. the section bip-8 byte is calculated on the scrambled bytes of the complete frame. the section bip- 8 byte is based on a bit interleaved parity calculation using even parity. the calculated bip-8 error detection code is inserted in the b1 byte of sts-1 (stm-0) #1 of the following frame before scrambling. 10.13 transmit tail trace processor (tttp) the transmit tail trace processor (tttp) block generates the tail trace messages to be transmitted. the tttp can generate a 16 or 64 byte tail trace message. the message is source from an internal ram and must have been previously written by an external micro processor. optionally, the tail trace message can be reduced to a single continuous tail trace byte.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 76 the tail trace message must include synchronisation because the tttp does not add synchronisation. the synchronisation mechanism is different for a 16 bytes message and for a 64 bytes message. when the message is 16 bytes, the synchronisation is based on the msb of the tail trace byte. only one of the 16 bytes has is msb set high. the byte with its msb set high is considered the first byte of the message. when the message is 64 bytes, the synchronisation is based on the cr/lf (cr = 0dh, lf = 0ah) characters of tail trace message. the byte following the cr/lf bytes is considered the first byte of the message. to avoid generating an unstable/mismatch message, the tttp forces the message to all zeros while the microprocessor updates the internal ram. 10.14 transmit high order path processor (thpp) the transmit high order path processor (thpp) block inserts the path overhead bytes in the transmit data stream. the thpp accumulates the path bip-8 errors detected by the rhpp during the last receive frame. the path bip-8 errors are returned to the far end as path remote error indication (rei-p) during the next transmit frame. because the rhpp and the thpp are in two different clock domains, none, one or two path bip-8 errors can be accumulated per transmit frame. the minimum value between the maximum rei-p and the accumulator count is returned as the path rei in the g1 byte. optionally, block bip-8 errors can be accumulated. the thpp serially inputs all the path overhead (poh) bytes from the tpoh port. the poh bytes must be input in the same order that they are transmitted (j1, b3, c2, g1, f2, h4, f3, k3 and n1). tohclk is the generated output clock used to provide timing for the tpoh port. tohclk is a nominal 20.736 mhz clock generated by gapping a 25.92 mhz clock. sampling tpohrdy high with the rising edge of tohclk identifies the msb of the first j1 byte. tpohen port is used to validate the byte insertion on a byte per byte basis. when tpohen is sampled high on the msb of the serial byte, the serial byte is inserted. when tpohen is sampled low on the msb of the serial byte, the serial byte is discarded. the thpp calculates the path bip-8 error detection code on the transmit data stream. the path bip-8 byte is calculated on all the payload bytes. the path bip-8 byte is based on a bit interleaved parity calculation using even parity. the calculated bip-8 error detection code is inserted in the b3 byte of the following frame. 10.15 transmit cell and frame processor (tcfp) the transmit cell and frame processor (tcfp) performs both atm and ppp processing. it has the capability to process a single sts-48c (stm-16c) channel. in atm mode, the tcfp performs provides rate adaptation via idle/unassigned cell insertion, provides hcs generation and insertion, and performs atm cell scrambling. in pos mode, the tcfp provides rate adaptation by transmitting flag sequences (0x7e) between packets, provides fcs generation and insertion, performs packet data scrambling, and provides performance monitoring functions.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 77 10.15.1 atm idle/unassigned cell generator the idle/unassigned cell generator inserts idle or unassigned cells into the cell stream when enabled. registers are provided to program the gfc, pti, and clp fields of the idle cell header and the idle cell payload. the idle cell hcs is automatically calculated and inserted. 10.15.2 atm scrambler the scrambler scrambles the 48 octet information field. scrambling is performed using a parallel implementation of the self-synchronous scrambler (x 43 + 1 polynomial) described in the references. the cell headers are transmitted unscrambled, and the scrambler may optionally be disabled. 10.15.3 atm hcs generator the hcs generator performs a crc-8 calculation over the first four header octets. a parallel implementation of the polynomial, x 8 +x 2 +x+1, is used. the coset polynomial, x 6 +x 4 +x 2 +1, is added (modulo 2) to the residue. the hcs generator optionally inserts the result into the fifth octet of the header. 10.15.4 pos ppp/hdlc frame generator the ppp/hdlc frame generator runs off of the sonet sequencer to create the pos frames to be transmitted. flags are inserted whenever the transmit fifo is empty and there is no data to transmit. when there is enough data to be transmitted, the block operates normally; it removes packets from the transmit fifo and transmits them. in addition, fcs generation, error insertion, byte stuffing, and scrambling can be optionally enabled. in the event of a fifo underflow caused by the fifo being empty while a packet is being transmitted, the packet is aborted by transmitting the abort sequence. the ppp abort sequence consists of an escape control character (0x7d) followed by the flag sequence (0x7e). bytes associated with this aborted frame are still read from the fifo but are discarded and replaced with the flag sequence in the outgoing data stream. if an overflow occurs, the packet being transmitted will also be aborted and the same abort sequence will be added. transmission of data resumes when a start of packet is encountered in the fifo data stream. the pos frame generator also performs inter packet gapping. this operation consists of inserting a programmable number of flag and idle sequence characters between each ppp/hdlc frame transmission. this feature allows one to control the system effective data transmission rate if required.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 78 10.15.5 pos fcs generator the fcs generator performs a crc-ccitt or crc-32 calculation on the whole pos frame, before byte stuffing and data scrambling. a parallel implementation of the crc polynomial is used. the crc algorithm for the frame checking sequence (fcs) field is either a crc-ccitt or crc-32 function. the crc-ccitt is two bytes in size and has a generating polynomial g(x) = 1 + x 5 + x 12 + x 16 . the crc-32 is four bytes in size and has a generating polynomial g(x) = 1 + x + x 2 + x 4 + x 5 + x 7 + x 8 + x 10 + x 11 + x 12 + x 16 + x 22 + x 23 + x 26 + x 32 . the first fcs bit transmitted is the coefficient of the highest term. when transmitting a packet from the transmit fifo, the fcs generator appends the result after the last data byte, before the closing flag. note that the frame check sequence is the one's complement of the crc register after calculation ends. fcs calculation and insertion can be disabled. figure 16: crc generator + d 0 + d 1 + + g n-1 g 2 g 1 message d n-1 . . . parity check digits lsb msb an error insertion mechanism is provided for system diagnosis purposes. error insertion is performed by inverting the resulting fcs value, before transmission. this should cause an fcs error at the far end. 10.15.6 pos byte stuffing the ppp frame generator provides transparency by performing byte stuffing. this operation is done after the fcs calculation. two characters are being escaped, the flag sequence (0x7e) and the escape character itself (0x7d). when a character is being escaped, it is xored with 0x20 before transmission and preceded by the control escape (0x7d) character. table 6: byte stuffing original escaped 7e (flag sequence) 7d-5e 7d (control escape) 7d-5d abort sequence 7d-7e
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 79 10.15.7 data scrambling the scrambler will optionally scramble the whole packet data, including the fcs and the flags. scrambling is performed after the pos frame is formed using a parallel implementation of the self-synchronous scrambler polynomial, x 43 +1. on reset, the scrambler is set to all ones to ensure scrambling on start-up. the scrambler may optionally be completely disabled. data scrambling can provide for a more robust system preventing the injection of hostile patterns into the data stream. 10.16 transmit scalable data queue (txsdq) the txsdq provides a fifo to separate the line-side timing from the higher layer atm/pos link layer timing. the txsdq has two modes of operations, atm and pos. 10.16.1 transmit atm fifo the txsdq is responsible for holding up to 48 cells until they can be read and transmitted. the cells are written in with a single 32-bit data bus running off tfclk and are read out at the channel rate. internal read and write pointers track the cells and indicate the fill status of the transmit fifo. separate read and write clock domains provide for separation of the physical layer line timing from the system link layer timing (tfclk). 10.16.2 transmit pos fifo the txsdq contains 48 sixteen byte blocks for fifo storage, along with management circuitry for reading and writing the fifo. octets are written in with a single 32-bit data bus running off tfclk and are read out with a single 32-bit data bus. separate read and write clock domains provide for separation of the physical layer line timing from the system link layer timing. internal read and write pointers track the insertion and removal of octets, and indicate the fill status of the transmit fifo. these status indications are used to detect underrun and overrun conditions, abort packets as appropriate on both system and line sides, control flag insertion and to generate the dtpa output. 10.17 transmit phy interfaces (rxphy and txphy) the s/uni-2488 transmit system interface can be configured for atm or pos mode. when configured for atm applications, the system interface provides a 32-bit transmit utopia level 3 compatible bus to allow the transfer of atm cells between the atm layer device and the s/uni- 2488. when configured for pos applications, the system interface provides either a 32-bit pos- phy level 3 compliant bus for the transfer of atm cells and data packets between the link layer device and the s/uni-2488. the link layer device can implement various protocols, including ppp and hdlc.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 80 10.17.1 transmit utopia level 3 interface the utopia level 3 compliant interface accepts a write clock (tfclk), a write enable signal (tenb), the start of a cell (tsoc) indication and the parity bit (tprty) when data is written to the transmit fifo (using the rising edges of the tfclk). to reduce fifo latency, the fifo depth at which tca indicates ?full? can be configured from the txsdq. if the programmed depth is less than the txsdq fifo capacity, more than one cell may be written after tca is deasserted as the txsdq fifo still allows the ?maximum? cells to be stored in its fifo. the interface provides the transmit cell available status (tca) which can transition from "available" to "unavailable" when the transmit fifo is near full or when the fifo is full and can accept no more writes. the tcfp cell processor automatically transmit idle cells until a full cell is available to be transmitted. 10.17.2 transmit pos-phy level 3 interface the pos-phy level 3 compliant interface accepts a write clock (tfclk), a write enable signal (tenb), the start of packet (tsop) indication, the end of packet (teop) indication, errored packet (terr) indication and the parity bit (tprty) when data is written to the transmit fifo (using the rising edges of the tfclk). the tpa signal notifies that the transmit fifo is not full (the pos processor will not start transmitting a packet until a programmable number of bytes for a single packet or the entire packet is in the fifo). the tmod signal (transmit mod) is provided to indicate whether 1, 2, 3, or 4 bytes are valid of the final word transfer (teop is asserted). a packet may be aborted by asserting the terr signal at the end of the packet. the interface also indicates fifo overruns via a maskable interrupt and register bits. the tcfp hdlc processor automatically transmits idle flag characters until sufficient data is available in the transmit txsdq to start transmission. 10.18 sonet/sdh bit error rate monitor (sber) the sber block provides two independent bit error rate monitoring circuits (berm block). it is used to monitor the multiplexer section bip (b1) with one berm block dedicated to monitor the signal degrade (sd) alarm and the other berm block dedicated to monitor the signal fail (sf) alarm. these alarm can then be used to control system level features such as automatic protection switching (aps). the berm block utilizes a sliding window based algorithm. 10.19 sonet/sdh alarm reporting controller (sarc) the sarc block receives all the section, line, and path defects detected by the receive overhead processors and, according to user specific configuration, generates consequent action indications.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 81 receive section alarm (rsalm) indication: rsalm is asserted when a oof, lof, los. ais-l, rdi-l, apsbf, tiu-s, tim-s, sdber or sfber defect is detected in the receive data stream. configuration registers allow the user to remove any defect from the previous enumeration. receive line ais insertion (rlaisins) indication: rlaisins is asserted when a oof, lof, los. ais-l, rdi-l, apsbf, tiu-s, tim-s, sdber or sfber defect is detected in the receive data stream. configuration register allow the user to remove any defect from the previous enumeration. transmit line rdi insertion (tlrdiins) indication: tlrdiins is asserted when a oof, lof, los. ais-l, rdi-l, apsbf, tiu-s, tim-s, sdber or sfber defect is detected in the receive data stream. configuration register allow the user to remove any defect from the previous enumeration. receive path alarm (rpalm) indication: rpalm is asserted when a rsalm, msrsalm, ais-p, lop-p, plu-p. plm-p, uneq-p, pdi-p, rdi-p, erdi-p, tiu-p or tim-p defect is detected in the receive data stream. configuration registers allow the user to remove any defect from the previous enumeration. receive path alarm insertion (rpaisins) indication: rpaisins is asserted when a rlaisins, msrlaisins, ais-p, lop-p, plu-p. plm-p, uneq-p, pdi-p, rdi-p, erdi-p, tiu-p or tim-p defect is detected in the receive data stream. configuration registers allow the user to remove any defect from the previous enumeration. transmit path erdi insertion (tperdiins[2:0]) indication: tperdiins[2:0] is updated when a plu-p, plm-p, tiu-p, tim-p, uneq-p, lop-p or a ais-p defect is detected in the receive data stream. configuration register allow the user to remove any defect from the previous enumeration. 10.20 sonet/sdh inband error report processor (sirp) the sirp block is used for error reporting from a remote aps protect mate when operating as the working mate under a failure condition. when in the failure condition, the remote protect mate performs section, line and path termination and passes the expected p-rei and p-rdi indications back to the working mate in-band in the g1 byte via its output aps port. the sirp block processes remote alarm indications in the sonet/sdh data stream from the input aps port. the sirp in the companion working mate can be configured to extract remote defect indications (rdi) and remote error indications (rei) from a sts-48c (stm-4c) incoming data stream. accumulated remote error indications and remote defect indications are reported to the thpp block. both rdi and extended rdi modes are available. the rdi report can be configured to be maintained asserted for at least 10 frames or 20 frames.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 82 10.21 aps serial data interface the aps serial data interface consists of a input and output 777.76 mbps serial telecombus used to communicate between a working and protect mate for aps applications. 10.21.1 output aps serial data interface (d8e, apiso, txlv) the output aps serial data interface uses the four sets of d8e, apiso and txlv blocks to transmit a sonet (sdh) stream to a working or protect mate. the sonet (sdh) oc-48 stream is selected from either the thpp or svca block and serialized on a 777.76 mbps serial telecombus. when the s/uni-2488 is configured as the working mate, the output aps serial data interface selects the transmit path processed sonet (sdh) stream from the thpp block and transmits it through the 4 differential lvds pairs, apso+/-[4:1] to the protect mate where the stream is line and section processed. when the s/uni-2488 is configured as the protect mate, the output aps serial data interface selects receive path terminated sonet (sdh) stream from the svca block and transmit it through the 4 differential lvds pairs, apso+/-[4:1] to the working mate. the working mate will then process the sonet (sdh) payload (atm or pos) and pass the results to the system via the utopia level 3 or posphy level 3 interface. there are four sets of de8, apiso and txlv blocks. each set implements one of four serial streams that make up the output serial telecombus. the d8e block takes a sonet (sdh) stream and 8b/10b encodes it. the apiso block performs a parallel to serial conversion. the txlv block is a differential lvds transmitter. 10.21.2 input aps serial data interface (rxlv, dru, r8tb) the input aps serial data interface uses the four sets of rxlv, dru and r8tb blocks to receive a sonet (sdh) stream from a working or protect mate via a serial telecombus. the received sonet (sdh) oc-48 stream is passed to either the rcfp or trmp block for further processing. when the s/uni-2488 is configured as the working mate and when a failure condition exists, a receive path processed sonet (sdh) stream is expected from the protect mate on the 4 differential lvds pairs, apsi+/-[4:1]. the s/uni-2488 will pass this received stream to the rcfp for atm or pos payload processing. when the s/uni-2488 is configured as the protect mate and when a failure condition exists, a transmit path processed sonet (sdh) stream is expected from the working mate on the 4 differential lvds pairs, apsi+/-[4:1]. the s/uni-2488 will pass this received stream to the trmp for sonet line and section insertion before it is transmitted. there are four sets of rxlv, dru and r8tb blocks. each set implements one of four serial streams that make up the input serial telecombus. the rxlv block is a differential lvds receiver. the dru recovers the 777.76 mbps 8b/10b encoded serial stream and deserializes it for the r8tb block. the r8tb block converts the deserialized 8b/10b stream into the a sonet (sdh) stream.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 83 10.21.3 lvds transmit reference (txref) the txlvref provides an on-chip bandgap voltage reference (1.20v 5%) and a precision current to the txlvs. the reference voltage is used to control the common-mode level of the txlv output, while the reference current is used to control the output amplitude. the precision currents are generated by forcing the reference voltage across an external, off-chip 4.75k ? (1%) resistor. the resulting current is then mirrored through several individual reference current outputs, so each txlv receives its own reference current. 10.21.4 clock synthesis unit (csu) the csu is a fully integrated clock synthesis unit. it generates low jitter multi-phase differential clocks at 777.6 mhz for the usage by the transmitter. 10.22 jtag test access port interface the jtag test access port block provides jtag support for boundary scan. the standard jtag extest, sample, bypass, idcode and stctest instructions are supported. the s/uni-2488 identification code is 053810cd hexadecimal. 10.23 microprocessor interface the microprocessor interface block provides the logic required to interface the generic microprocessor bus with the normal mode and test mode registers within the s/uni-2488. the normal mode registers are used during normal operation to configure and monitor the s/uni-2488. the test mode registers are used to enhance the testability of the s/uni-2488. the register set is accessed as shown below. the corresponding memory map address is identified by the address column of the table. addresses that are not shown are not used and must be treated as reserved. table 7: register memory map address register description 0000 s/uni-2488 identity, and global performance monitor update 0001 s/uni-2488 master reset, configuration, and loopback 0002 s/uni-2488 reserved 0003 s/uni-2488 clock monitors 0004 s/uni-2488 master interrupt status #1 0005 s/uni-2488 master interrupt status #2 0006 s/uni-2488 master interrupt status #3 0007 s/uni-2488 master interrupt status #4 0008 s/uni-2488 master interrupt status #5 0009 s/uni-2488 master interrupt status #6 000a s/uni-2488 master interrupt status #8 000b unused
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 84 address register description 000c s/uni-2488 aps input telecombus synchronization delay 000d s/uni-2488 aps output telecombus synchronization delay 000e s/uni-2488 diagnostics 000f s/uni-2488 free register 0010-001f rx2488 analog reserved 0020-002f tx2488 analog reserved 0030 srli clock configuration 0031 srli pgm clock configuration 0032-0037 srli reserved 0038 stli clock configuration 0039 stli pgm clock configuration 003a-003f stli reserved 0040 rrmp configuration 0041 rrmp status 0042 rrmp interrupt enable 0043 rrmp interrupt status 0044 rrmp received aps 0045 rrmp received ssm 0046 rrmp ais enable 0047 rrmp section bip error counter 0048 rrmp line bip error counter (lsb) 0049 rrmp line bip error counter (msb) 004a rrmp line rei error counter (lsb) 004b rrmp line rei error counter (msb) 004c-004fh rrmp reserved 1 0050-005fh rrmp reserved 2 0060-006fh rrmp reserved 3 0070-007fh rrmp reserved 4 0080 trmp configuration 0081 trmp register insertion 0082 trmp error insertion 0083 trmp transmit j0 and z0 0084 trmp transmit e1 and f1 0085 trmp transmit d1d3 and d4d12 0086 trmp transmit k1 and k2 0087 trmp transmit s1 and z1 0088 trmp transmit z2 and e2
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 85 address register description 0089 trmp h1 and h2 mask 008a trmp b1 and b2 mask 008b-009f trmp reserved 1 00a0 trmp aux2 configuration 00a1 trmp reserved 2 00a2 trmp aux2 error insertion 00a3-00bf trmp reserved 2 00c0 trmp aux3 configuration 00c1 trmp reserved 3 00c2 trmp aux3 error insertion 00c3-00df trmp reserved 3 00e0 trmp aux4 configuration 00e1 trmp reserved 4 00e2 trmp aux4 error insertion 00e3-00ff trmp reserved 4 0100-010f s/uni-2488 reserved 0110 sber configuration 0111 sber status 0112 sber interrupt enable 0113 sber interrupt status 0114 sber sf berm accumulation period (lsb) 0115 sber sf berm accumulation period (msb) 0116 sber sf berm saturation threshold (lsb) 0117 sber sf berm saturation threshold (msb) 0118 sber sf berm declaring threshold (lsb) 0119 sber sf berm declaring threshold (msb) 011a sber sf berm clearing threshold (lsb) 011b sber sf berm clearing threshold (msb) 011c sber sd berm accumulation period (lsb) 011d sber sd berm accumulation period (msb) 011e sber sd berm saturation threshold (lsb) 011f sber sd berm saturation threshold (msb) 0120 sber sd berm declaring threshold (lsb) 0121 sber sd berm declaring threshold (msb) 0122 sber sd berm clearing threshold (lsb) 0123 sber sd berm clearing threshold (msb) 0124-012f sber reserved
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 86 address register description 0130 rttp section indirect address 0131 rttp section indirect data 0132 rttp section trace unstable status 0133 rttp section trace unstable interrupt enable 0134 rttp section trace unstable interrupt status 0135 rttp section trace mismatch status 0136 rttp section trace mismatch interrupt enable 0137 rttp section trace mismatch interrupt status 0138 tttp section indirect address 0139 tttp section indirect data 013a-013b tttp section reserved 013c-01ff s/uni-2488 reserved 0200 rhpp sts-1/stm-0 #1 through #12 indirect address 0201 rhpp sts-1/stm-0 #1 through #12 indirect data 0202-0207 rhpp reserved 0208 rhpp sts-1/stm-0 #1 pointer interpreter status 0209 rhpp sts-1/stm-0 #1 pointer interpreter interrupt enable 020a rhpp sts-1/stm-0 #1 pointer interpreter interrupt status 020b rhpp sts-1/stm-0 #1 error monitor status 020c rhpp sts-1/stm-0 #1 error monitor interrupt enable 020d rhpp sts-1/stm-0 #1 error monitor interrupt status 020e rhpp sts-1/stm-0 #1 path bip error counter 020f rhpp sts-1/stm-0 #1 path rei error counter 0210 rhpp sts-1/stm-0 #2 pointer interpreter status 0211 rhpp sts-1/stm-0 #2 pointer interpreter interrupt enable 0212 rhpp sts-1/stm-0 #2 pointer interpreter interrupt status 0213-0217 rhpp reserved 0218 rhpp sts-1/stm-0 #3 pointer interpreter status 0219 rhpp sts-1/stm-0 #3 pointer interpreter interrupt enable 021a rhpp sts-1/stm-0 #3 pointer interpreter interrupt status 021b-021f rhpp reserved 0220 rhpp sts-1/stm-0 #4 pointer interpreter status 0221 rhpp sts-1/stm-0 #4 pointer interpreter interrupt enable 0222 rhpp sts-1/stm-0 #4 pointer interpreter interrupt status 0223-0227 rhpp reserved 0228 rhpp sts-1/stm-0 #5 pointer interpreter status 0229 rhpp sts-1/stm-0 #5 pointer interpreter interrupt enable
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 87 address register description 022a rhpp sts-1/stm-0 #5 pointer interpreter interrupt status 022b-022f rhpp reserved 0230 rhpp sts-1/stm-0 #6 pointer interpreter status 0231 rhpp sts-1/stm-0 #6 pointer interpreter interrupt enable 0232 rhpp sts-1/stm-0 #6 pointer interpreter interrupt status 0233-0237 rhpp reserved 0238 rhpp sts-1/stm-0 #7 pointer interpreter status 0239 rhpp sts-1/stm-0 #7 pointer interpreter interrupt enable 023a rhpp sts-1/stm-0 #7 pointer interpreter interrupt status 023b-023f rhpp reserved 0240 rhpp sts-1/stm-0 #8 pointer interpreter status 0241 rhpp sts-1/stm-0 #8 pointer interpreter interrupt enable 0242 rhpp sts-1/stm-0 #8 pointer interpreter interrupt status 0243-0247 rhpp reserved 0248 rhpp sts-1/stm-0 #9 pointer interpreter status 0249 rhpp sts-1/stm-0 #9 pointer interpreter interrupt enable 024a rhpp sts-1/stm-0 #9 pointer interpreter interrupt status 024b-024f rhpp reserved 0250 rhpp sts-1/stm-0 #10 pointer interpreter status 0251 rhpp sts-1/stm-0 #10 pointer interpreter interrupt enable 0252 rhpp sts-1/stm-0 #10 pointer interpreter interrupt status 0253-0257 rhpp reserved 0258 rhpp sts-1/stm-0 #11 pointer interpreter status 0259 rhpp sts-1/stm-0 #11 pointer interpreter interrupt enable 025a rhpp sts-1/stm-0 #11 pointer interpreter interrupt status 025b-025f rhpp reserved 0260 rhpp sts-1/stm-0 #12 pointer interpreter status 0261 rhpp sts-1/stm-0 #12 pointer interpreter interrupt enable 0262 rhpp sts-1/stm-0 #12 pointer interpreter interrupt status 0263-027f rhpp reserved 0280 rhpp sts-1/stm-0 #13 through #24 indirect address 0281 rhpp sts-1/stm-0 #13 through #24 indirect data 0282-0287 rhpp reserved 0288 rhpp sts-1/stm-0 #13 pointer interpreter status 0289 rhpp sts-1/stm-0 #13 pointer interpreter interrupt enable 028a rhpp sts-1/stm-0 #13 pointer interpreter interrupt status 028b-028f rhpp reserved
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 88 address register description . . . . . . . . . . . . . . . . . . . . 02e0 rhpp sts-1/stm-0 #24 pointer interpreter status 02e1 rhpp sts-1/stm-0 #24 pointer interpreter interrupt enable 02e2 rhpp sts-1/stm-0 #24 pointer interpreter interrupt status 02e3-02ff rhpp reserved 0300 rhpp sts-1/stm-0 #25 through #36 indirect address 0301 rhpp sts-1/stm-0 #25 through #36 indirect data 0302-0307 rhpp reserved 0308 rhpp sts-1/stm-0 #25 pointer interpreter status 0309 rhpp sts-1/stm-0 #25 pointer interpreter interrupt enable 030a rhpp sts-1/stm-0 #25 pointer interpreter interrupt status 030b-030f rhpp reserved . . . . . . . . . . . . . . . . . . . . 0360 rhpp sts-1/stm-0 #36 pointer interpreter status 0361 rhpp sts-1/stm-0 #36 pointer interpreter interrupt enable 0362 rhpp sts-1/stm-0 #36 pointer interpreter interrupt status 0363-036f rhpp reserved 0380 rhpp sts-1/stm-0 #37 through #48 indirect address 0381 rhpp sts-1/stm-0 #37 through #48 indirect data 0382-0387 rhpp reserved 0388 rhpp sts-1/stm-0 #37 pointer interpreter status 0389 rhpp sts-1/stm-0 #37 pointer interpreter interrupt enable 038a rhpp sts-1/stm-0 #37 pointer interpreter interrupt status 038b-038f rhpp reserved . . . . . . . . . . . . . . . . . . . . 03e0 rhpp sts-1/stm-0 #48 pointer interpreter status 03e1 rhpp sts-1/stm-0 #48 pointer interpreter interrupt enable 03e2 rhpp sts-1/stm-0 #48 pointer interpreter interrupt status 03e3-03ff rhpp reserved 0400 thpp sts-1/stm-0 #1 through #12 indirect address 0401 thpp sts-1/stm-0 #1 through #12 indirect data 0402 thpp payload configuration 0402-047f thpp reserved 1 0480 thpp sts-1/stm-0 #13 through #24 indirect address 0481 thpp sts-1/stm-0 #13 through #24 indirect data 0482-04ff thpp reserved 2 0500 thpp sts-1/stm-0 #25 through #36 indirect address
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 89 address register description 0501 thpp sts-1/stm-0 #25 through #36 indirect data 0502-057f thpp reserved 3 0580 thpp sts-1/stm-0 #37 through #48 indirect address 0581 thpp sts-1/stm-0 #37 through #48 indirect data 0582-05ff thpp reserved 4 0600 rsvca indirect address 0601 rsvca indirect data 0602 rsvca payload configuration 0603 rsvca positive justification interrupt status 0604 rsvca negative justification interrupt status 0605 rsvca fifo overflow interrupt status 0606 rsvca fifo underflow interrupt status 0607-061f rsvca reserved 1 0620-063f rsvca reserved 2 0640-065f rsvca reserved 3 0660-067f rsvca reserved 4 0680 tsvca indirect address 0681 tsvca indirect data 0682 tsvca payload configuration 0683 tsvca positive justification interrupt status 0684 tsvca negative justification interrupt status 0685 tsvca fifo overflow interrupt status 0686 tsvca fifo underflow interrupt status 0687-069f tsvca reserved 1 06a0-06bf tsvca reserved 2 06c0-06df tsvca reserved 3 06e0-06ff tsvca reserved 4 0700 rttp path indirect address 0701 rttp path indirect data 0702 rttp path trace unstable status 0703 rttp path trace unstable interrupt enable 0704 rttp path trace unstable interrupt status 0705 rttp path trace mismatch status 0706 rttp path trace mismatch interrupt enable 0707 rttp path trace mismatch interrupt status 0708 tttp path indirect address 0709 tttp path indirect data
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 90 address register description 070a-070b tttp path reserved 070c-071f s/uni-2488 reserved 0720 sarc indirect address 0721 sarc reserved 0722 sarc section configuration 0723 sarc section salm 0724 sarc section rlaisins enable 0725 sarc section tlaisins enable 0726-0727 sarc reserved 0728 sarc path configuration 0729 sarc path ralm enable 072a sarc path rpaisins enable 072b-072f sarc reserved 0730 sarc lop pointer status 0731 sarc lop pointer interrupt enable 0732 sarc lop pointer interrupt status 0733 sarc ais pointer status 0734 sarc ais pointer interrupt enable 0735 sarc ais pointer interrupt status 0736-073f sarc reserved 0740 rcfp configuration 0741 rcfp interrupt enable 0742 rcfp interrupt indication and status 0743 rcfp minimum packet length 0744 rcfp maximum packet length 0745 rcfp lcd count threshold 0746 rcfp idle cell header and mask 0747 rcfp receive byte/idle cell counter (lsb) 0748 rcfp receive byte/idle cell counter 0749 rcfp receive byte/idle cell counter (msb) 074a rcfp packet/cell counter (lsb) 074b rcfp receive packet/atm cell counter (msb) 074c rcfp receive erred fcs/hcs counter 074d rcfp receive aborted packet counter 074e rcfp receive minimum length packet error 074f rcfp receive maximum length packet error counter 0750 tcfp configuration
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 91 address register description 0751 tcfp interrupt indication 0752 tcfp idle/unassigned atm cell header 0753 tcfp diagnostics 0754 tcfp transmit cell/packet counter (lsb) 0755 tcfp transmit cell/packet counter (msb) 0756 tcfp transmit byte counter (lsb) 0757 tcfp transmit byte counter 0758 tcfp transmit byte counter (msb) 0759 tcfp aborted packet counter 075a-075f tcfp reserved 0760 rxsdq fifo reset 0761 rxsdq fifo interrupt enable 0762 rxsdq reserved 0763 rxsdq fifo overflow port and interrupt indication 0764 rxsdq fifo sop error port and interrupt indication 0765 rxsdq fifo eop error port and interrupt indication 0766 rxsdq reserved 0767 rxsdq reserved 0768 rxsdq fifo indirect address 0769 rxsdq fifo indirect configuration 076a rxsdq fifo indirect data available threshold 076b rxsdq fifo indirect cells and packets count 076c rxsdq fifo cells and packets accepted aggregate count (lsb) 076d rxsdq fifo cells and packets accepted aggregate count (msb) 076e rxsdq fifo cells and packets dropped aggregate count 076f rxsdq reserved 0770 txsdq fifo reset 0771 txsdq fifo interrupt enable 0772 txsdq reserved 0773 txsdq fifo overflow port and interrupt indication 0774 txsdq fifo sop error port and interrupt indication 0775 txsdq fifo eop error port and interrupt indication 0776 txsdq reserved 0777 txsdq reserved 0778 txsdq fifo indirect address 0779 txsdq fifo indirect configuration 077a txsdq fifo indirect data and buffer available thresholds
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 92 address register description 077b txsdq fifo indirect cells and packets count 077c txsdq fifo cells and packets accepted aggregate count (lsb) 077d txsdq fifo cells and packets accepted aggregate count (msb) 077e txsdq fifo cells and packets dropped aggregate count 077f txsdq reserved 0780 rxphy configuration 0781 rxphy interrupt status 0782 rxphy interrupt enable 0783 rxphy indirect burst size 0784 rxphy calendar length 0785 rxphy calendar indirect address data 0786 rxphy data type field 0787 rxphy reserved 0788 txphy configuration 0789 txphy interrupt status 078a txphy interrupt enable 078b txphy data type field 078c-078f txphy reserved 0790 sirp configuration timeslot 0791-079b sirp reserved 1 079c sirp configuration 079d-079f sirp reserved 1 07a0-07af sirp reserved 2 07b0-07bf sirp reserved 2 07c0-07cf sirp reserved 2 07d0-07ff s/uni-2488 reserved 0800 prgm indirect address 0801 prgm indirect data 0802 prgm generator payload configuration 0803 prgm monitor payload configuration 0804 prgm monitor byte error interrupt status 0805 prgm monitor byte error interrupt enable 0806 prgm monitor b1/e1 bytes interrupt status 0807 prgm monitor b1/e1 bytes interrupt enable 0808 prgm monitor b1/e1 bytes status 0809 prgm monitor synchronization interrupt status 080a prgm monitor synchronization interrupt enable
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 93 address register description 080b prgm monitor synchronization status 080c prgm reserved 080d-080f prgm reserved 0810 prgm aux2 indirect address 0811 prgm aux2 indirect data 0812 prgm aux2 generator payload configuration 0813 prgm aux2 monitor payload configuration 0814 prgm aux2 monitor byte error interrupt status 0815 prgm aux2 monitor byte error interrupt enable 0816-0818 prgm aux2 reserved 0819 prgm aux2 monitor synchronization interrupt status 081a prgm aux2 monitor synchronization interrupt enable 081b prgm aux2 monitor synchronization status 081c-081f prgm aux2 reserved 0820 prgm aux3 indirect address 0821 prgm aux3 indirect data 0822 prgm aux3 generator payload configuration 0823 prgm aux3 monitor payload configuration 0824 prgm aux3 monitor byte error interrupt status 0825 prgm aux3 monitor byte error interrupt enable 0826-0828 prgm aux3 reserved 0829 prgm aux3 monitor synchronization interrupt status 082a prgm aux3 monitor synchronization interrupt enable 082b prgm aux3 monitor synchronization status 082c-082f prgm aux3 reserved 0830 prgm aux3 indirect address 0831 prgm aux3 indirect data 0832 prgm aux4 generator payload configuration 0833 prgm aux4 monitor payload configuration 0834 prgm aux4 monitor byte error interrupt status 0835 prgm aux4 monitor byte error interrupt enable 0836-0838 prgm aux4 reserved 0839 prgm aux4 monitor synchronization interrupt status 083a prgm aux4 monitor synchronization interrupt enable 083b prgm aux4 monitor synchronization status 083c-083f prgm aux4 reserved 0840 r8td aps0 control and status
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 94 address register description 0841 r8td aps0 interrupt status 0842 r8td aps0 line code violation count 0843 r8td aps0 analog control 1 0844 r8td aps0 analog control 2 0845-0847 r8td aps0 reserved 0848 r8td aps1 control and status 0849 r8td aps1 interrupt status 084a r8td aps1 line code violation count 084b r8td aps1 analog control 1 084c r8td aps1 analog control 2 084d-084f r8td aps1 reserved 0850 r8td aps2 control and status 0851 r8td aps2 interrupt status 0852 r8td aps2 line code violation count 0853 r8td aps2 analog control 1 0854 r8td aps2 analog control 2 0855-0857 r8td aps2 reserved 0858 r8td aps3 control and status 0859 r8td aps3 interrupt status 085a r8td aps3 line code violation count 085b r8td aps3 analog control 1 085c r8td aps3 analog control 2 085d-085f r8td aps3 reserved 0860 t8te aps0 control and status 0861 t8te aps0 interrupt status 0862 t8te aps0 telecombus mode #1 0863 t8te aps0 telecombus mode #2 0864 t8te aps0 test pattern 0865 t8te aps0 analog control 0866 t8te aps0 dtb bus 0867 t8te aps0 reserved 0868 t8te aps1 control and status 0869 t8te aps1 interrupt status 086a t8te aps1 telecombus mode #1 086b t8te aps1 telecombus mode #2 086c t8te aps1 test pattern 086d t8te aps1 analog control
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 95 address register description 086e t8te aps1 dtb bus 086f t8te aps1 reserved 0870 t8te aps2 control and status 0871 t8te aps2 interrupt status 0872 t8te aps2 telecombus mode #1 0873 t8te aps2 telecombus mode #2 0874 t8te aps2 test pattern 0875 t8te aps2 analog control 0876 t8te aps2 dtb bus 0877 t8te aps2 reserved 0878 t8te aps3 control and status 0879 t8te aps3 interrupt status 087a t8te aps3 telecombus mode #1 087b t8te aps3 telecombus mode #2 087c t8te aps3 test pattern 087d t8te aps3 analog control 087e t8te aps3 dtb bus 087f t8te aps3 reserved 0880-0883 rfclk dll reserved 0884-0887 tfclk dll reserved 0888 cstr control 0889 cstr interrupt enable and csu lock status 088a cstr csu lock interrupt indication 088b cstr reserved 088c-088f s/uni-2488 reserved 0890-0897 s/uni-2488 rx stsi reserved 0898-089f s/uni-2488 tx stsi reserved 08a0-1fff s/uni-2488 reserved 2000-2fff s/uni-2488 test notes on register memory map: 1. for all register accesses, csb must be low. 2. addresses that are not shown must be treated as reserved. 3. a[13] is the test resister select (trs) and should be set to logic 0 for normal mode register access.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 96
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 97 11 normal mode register description normal mode registers are used to configure and monitor the operation of the s/uni-2488. normal mode registers (as opposed to test mode registers) are selected when trs (a[13]) is low. notes on normal mode register bits: 1. writing values into unused register bits has no effect. however, to ensure software compatibility with future, feature-enhanced versions of this product, unused register bits must be written with logic 0. reading back unused bits can produce either a logic 1 or a logic 0; hence, unused register bits should be masked off by software when read. 2. all configuration bits that can be written into can also be read back. this allows the processor controlling the s/uni-2488 to determine the programming state of the device. 3. writeable normal mode register bits are cleared to logic 0 upon reset unless otherwise noted. 4. writing into read-only normal mode register bit locations does not affect s/uni-2488 operation unless otherwise noted. 5. certain register bits are reserved. these bits are associated with megacell functions that are unused in this application. to ensure that the s/uni-2488 operates as intended, reserved register bits must only be written with the logic level as specified. writing to reserved registers should be avoided.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 98 register 0000h: s/uni-2488 identity, and global performance monitor update bit type function default bit 15 r tip x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 r type[4] 0 bit 7 r type[3] 0 bit 6 r type[2] 0 bit 5 r type[1] 1 bit 4 r type[0] 0 bit 3 r id[3] 0 bit 2 r id[2] 0 bit 1 r id[1] 0 bit 0 r id[0] 0 this register allows the revision number of the s/uni-2488 to be read by software permitting graceful migration to newer, feature-enhanced versions of the s/uni-2488. in addition, writing to this register performs a global performance monitor update by simultaneously loading all the performance meter registers in the rhpp, rrmp, rcfp, rxsdq, txsdq, tcfp, r8td, and t8te blocks. id[3:0]: the id bits can be read to provide a binary s/uni-2488 revision number. type[4:0]: the type bits can be read to distinguish the s/uni-2488 from the other members of the family of devices. the type[4:0] register for the pm5381 s/uni-2488 is 00010. tip: the tip bit is set to a logic one when the performance meter registers are being loaded. writing to this register with dreset equal to logic 0 initiates an accumulation interval transfer and loads all the performance meter registers in the s/uni-2488. tip remains high while the transfer is in progress, and is set to a logic zero when the transfer is complete. tip can be polled by a microprocessor to determine when the accumulation interval transfer is complete.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 99 register 0001h: s/uni-2488 master reset, configuration, and loopback bit type function default bit 15 r/w dreset 0 bit 14 r/w areset 0 bit 13 r/w txdinv 0 bit 12 r/w rxdinv 0 bit 11 r/w discor 1 bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 r/w pl3en 0 bit 5 r/w mode[1] 0 bit 4 r/w mode[0] 0 bit 3 r/w loopt 0 bit 2 r/w pdle 0 bit 1 r/w sdle 0 bit 0 r/w slle 0 this register allows the configuration of s/uni-2488 features. slle: the slle bit enables the s/uni-2488 line loopback mode when the device is configured for 2488.32 mbit/s serial line interface mode of operation. when slle is a logic one, the recovered data from the receive serial rxd+/- differential inputs is mapped to the txd+/- differential outputs. the sdle and the slle bits should not be set high simultaneously. sdle: the sdle bit enables the serial diagnostic loopback. when sdle is a logic one, the transmit serial stream on the txd+/- differential outputs is internally connected to the received serial rxd+/- differential inputs. the sdle and the slle bits should not be set high simultaneously. pdle: the parallel diagnostic loopback, pdle bit enables the s/uni-2488 diagnostic loopback where the trmp block is directly connected to its rrmp block. when pdle is logic one, loopback is enabled. under this operating condition, the s/uni-2488 continues to operates
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 100 normally in the transmit direction. when pdle is logic zero, the s/uni-2488 operates normally. loopt: the loopt bit selects the source of timing for the transmit section of the channel. when loopt is a logic zero, the transmitter timing is derived from input refclk (clock synthesis unit). when loopt is a logic one, the transmitter timing is derived from the recovered clock (clock recovery unit). the s/uni-2488 cannot be configured for loop time operation if operating with a mate device unless both the received clocks are frequency locked. mode[1:0]: the mode bits selects one of the four operating mode of the s/uni-2488 as illustrated below: mode[1:0] description 00 normal operation. the s/uni-2488 is configured in this mode when not using the aps ports. when using the aps ports, the s/uni- 2488 is configured in this mode if a failover condition does not exist. under this mode of operation, the s/uni-2488 receives data from rxd+/- and outputs this data though its pos-phy level 3 interface and transmits data from its pos-phy level 3 interface out through txd+/-. 01 reserved 10 aps working mate under a failed condition. the s/uni-2488 can be configured in this mode when operating as the working device in a aps failover condition. under this mode of operation, the s/uni-2488 receives a sonet stream from a protect mate via the input aps port and presents the payload out through the pos-phy level 3 interface. the s/uni- 2488 transmits data from its pos-phy level 3 interface out thorough its output aps port to a mate device. it is assumed that the mate device will transmit the data onto the line. 11 aps protect mate. the s/uni-2488 is always configured in this mode as a protect device. under this mode of operation, the input aps port is expected to contain a bridged transmit sonet stream from a working mate device. in addition, the s/uni-2488 will output a received sonet stream out the output aps port to the same mate device.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 101 pl3en: the pos-phy level 3 select bit (posl3) is or?ed with the posl3_ul3b pin to select pos- phy level 3 mode on the system interface. when posl3 or posl3_ul3b are logic 1, the system bus operates in pos-phy level 3 mode. when both posl3 and posl3_ul3b are logic 0, the bus operates as a utopia level 3 bus. reading this bit gives the mode of the bus, (ie, the or of the pin and the bit). the default state of this register bit is logic 0. discor: the discor bit is used to globally disable atm single-bit hcs error correction. when discor is set to logic 1, hcs error correction is globally disabled. when discor is set to logic 0, hcs error correction is dependent on the rcfp configuration register. by default, hcs error correction is enabled in the rcfp. rxdinv: the receive inversion rxdinv bit controls the polarity of the receive data. when rxdinv is set high, the polarity of the rxd+/- is inverted. when rxdinv is set low, the rxd+/- inputs operate normally. txdinv: the transmit inversion txdinv bit controls the polarity of the transmit data. when txdinv is set high, the polarity of the txd+/- is inverted. when txdinv is set low, the txd+/- outputs operate normally. areset: the areset bit allows the analog circuitry in the s/uni-2488 to be reset under software control. if the areset bit is a logic one, all the s/uni-2488 analog circuitry is held in reset. this bit is not self-clearing. therefore, a logic zero must be written to bring the s/uni-2488 out of reset. holding the s/uni-2488 in a reset state places it into a low power, analog stand- by mode. a hardware reset clears the areset bit, thus negating the analog software reset. dreset: the dreset bit allows the digital circuitry in the s/uni-2488 to be reset under software control. if the dreset bit is a logic one, all the s/uni-2488 digital circuitry is held in reset. this bit is not self-clearing. therefore, a logic zero must be written to bring the s/uni-2488 out of reset a hardware reset clears the dreset bit, thus negating the digital software reset.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 102 register 0003h: s/uni-2488 clock monitors bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r tclka x bit 3 r rclka x bit 2 r rfclka x bit 1 r tfclka x bit 0 r refclka x refclka: the refclk active (refclka) bit monitors for low to high transitions on the refclk reference clock input. refclka is set high on a rising edge of refclk, and is set low when this register is read. tfclka: the tfclk active (tfclka) bit monitors for low to high transitions on the tfclk transmit fifo clock input. tfclka is set high on a rising edge of tfclk, and is set low when this register is read. rfclka: the rfclk active (rfclka) bit monitors for low to high transitions on the rfclk receive fifo clock input. rfclka is set high on a rising edge of rfclk, and is set low when this register is read. rclka: the rclk active (rclka) bit monitors for low to high transitions on the rclk output. rclka is set high on a rising edge of rclk, and is set low when this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 103 tclka: the tclk active (tclka) bit monitors for low to high transitions on the tclk output. tclka is set high on a rising edge of tclk, and is set low when this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 104 register 0004h: s/uni-2488 master interrupt status #1 bit type function default bit 15 r/w inte[1] 0 bit 14 r tstsii x bit 13 r unused x bit 12 r tprgmi[1] x bit 11 r tsvcai[1] x bit 10 r rstsii x bit 9 r rprgmi[1] x bit 8 r sarci[1] x bit 7 r rsvcai[1] x bit 6 r unused x bit 5 r unused x bit 4 r pathrttpi[1] x bit 3 r rhppi[1] x bit 2 r sberi[1] x bit 1 r rttpi[1] x bit 0 r rrmpi[1] x this register allows the source of an active interrupt to be identified down to the block level. further register accesses are required for the block in question to determine the cause of an active interrupt and to acknowledge the interrupt source. rrmpi[1]?tstsi: the rrmpi[1] to tstsi are interrupt status indicators for the corresponding block. the interrupt status is set to logic 1 to indicate a pending interrupt from the corresponding block. the interrupt status bits are independent of the interrupt enable bit. inte[1]: the interrupt enable (inte[1]) bit controls the assertion of the interrupt (intb) output. when a logic 1 is written to inte[1], the rrmp[1]?astsi pending interrupt will assert the interrupt (intb) output. when a logic 0 is written to inte[1], the rrmp[1]?tstsi pending interrupt will not assert the interrupt (intb) output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 105 register 0005h: s/uni-2488 master interrupt status #2 bit type function default bit 15 r/w inte[2] 0 bit 14 r unused x bit 13 r unused x bit 12 r tprgmi[2] x bit 11 r tsvcai[2] x bit 10 r unused x bit 9 r rprgmi[2] x bit 8 r sarci[2] x bit 7 r rsvcai[2] x bit 6 r unused x bit 5 r unused x bit 4 r unused x bit 3 r rhppi[2] x bit 2 r sberi[2] x bit 1 r rttpi[2] x bit 0 r rrmpi[2] x this register allows the source of an active interrupt to be identified down to the block level. further register accesses are required for the block in question to determine the cause of an active interrupt and to acknowledge the interrupt source. rrmpi[2]?tprgmi[2]: the rrmpi[2] to tprgmi[2] are interrupt status indicators for the corresponding block. the interrupt status is set to logic 1 to indicate a pending interrupt from the corresponding block. the interrupt status bits are independent of the interrupt enable bit. inte[2]: the interrupt enable (inte[2]) bit controls the assertion of the interrupt (intb) output. when a logic 1 is written to inte[2], the rrmp[2]?tprgm[2] pending interrupt will assert the interrupt (intb) output. when a logic 0 is written to inte[2], the rrmp[2]?tprgm[2] pending interrupt will not assert the interrupt (intb) output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 106 register 0006h: s/uni-2488 master interrupt status #3 bit type function default bit 15 r/w inte[3] 0 bit 14 r unused x bit 13 r unused x bit 12 r tprgmi[3] x bit 11 r tsvcai[3] x bit 10 r unused x bit 9 r rprgmi[3] x bit 8 r sarci[3] x bit 7 r rsvcai[3] x bit 6 r unused x bit 5 r unused x bit 4 r unused x bit 3 r rhppi[3] x bit 2 r sberi[3] x bit 1 r rttpi[3] x bit 0 r rrmpi[3] x this register allows the source of an active interrupt to be identified down to the block level. further register accesses are required for the block in question to determine the cause of an active interrupt and to acknowledge the interrupt source. rrmpi[3]?tprgmi[3]: the rrmpi[3] to tprgmi[3] are interrupt status indicators for the corresponding block. the interrupt status is set to logic 1 to indicate a pending interrupt from the corresponding block. the interrupt status bits are independent of the interrupt enable bit. inte[3]: the interrupt enable (inte[3]) bit controls the assertion of the interrupt (intb) output. when a logic 1 is written to inte[3], the rrmp[3]?tprgm[3] pending interrupt will assert the interrupt (intb) output. when a logic 0 is written to inte[3], the rrmp[3]?tprgm[3] pending interrupt will not assert the interrupt (intb) output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 107 register 0007h: s/uni-2488 master interrupt status #4 bit type function default bit 15 r/w inte[4] 0 bit 14 r unused x bit 13 r unused x bit 12 r tprgmi[4] x bit 11 r tsvcai[4] x bit 10 r unused x bit 9 r rprgmi[4] x bit 8 r sarci[4] x bit 7 r rsvcai[4] x bit 6 r unused x bit 5 r unused x bit 4 r unused x bit 3 r rhppi[4] x bit 2 r sberi[4] x bit 1 r rttpi[4] x bit 0 r rrmpi[4] x this register allows the source of an active interrupt to be identified down to the block level. further register accesses are required for the block in question to determine the cause of an active interrupt and to acknowledge the interrupt source. rrmpi[4]?tprgmi[4]: the rrmpi[4] to tprgmi[4] are interrupt status indicators for the corresponding block. the interrupt status is set to logic 1 to indicate a pending interrupt from the corresponding block. the interrupt status bits are independent of the interrupt enable bit. inte[4]: the interrupt enable (inte[4]) bit controls the assertion of the interrupt (intb) output. when a logic 1 is written to inte[4], the rrmp[4]?tprgm[4] pending interrupt will assert the interrupt (intb) output. when a logic 0 is written to inte[4], the rrmp[4]?tprgm[4] pending interrupt will not assert the interrupt (intb) output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 108 register 0008h: s/uni-2488 master interrupt status #5 bit type function default bit 15 r/w inte[5] 0 bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 r rxphyi x bit 8 r rxsdqi x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r rcfpi x this register is used to indicate interrupts generated from blocks associated with the receive utopia/pos-phy interfaces, fifo, and cell/frame processors. rcfpi: the rcfp interrupt event indication (rcfpi) transitions to logic 1 when a hardware interrupt event is sourced from rcfp # x block. this bit is cleared to logic 0 when the interrupt is cleared. rxsdqi: the rxsdq interrupt event indication (rxsdqi) transitions to logic 1 when a hardware interrupt event is sourced from the receive system fifo rxsdq block. this bit is cleared to logic 0 when the interrupt is cleared. rxphyi: the rxphy interrupt event indication (rxphyi) transitions to logic 1 when a hardware interrupt event is sourced from the receive system utopia/pos-phy interface rxphy block. this bit is cleared to logic 0 when the interrupt is cleared.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 109 inte[5]: the interrupt enable (inte[5]) bit controls the assertion of the interrupt (intb) output. when a logic 1 is written to inte[5], the rcfpi, rxsdqi or rxphyi pending interrupt will assert the interrupt (intb) output. when a logic 0 is written to inte[5], the rcfpi, rxsdqi or rxphyi pending interrupt will not assert the interrupt (intb) output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 110 register 0009h: s/uni-2488 master interrupt status #6 bit type function default bit 15 r/w inte[6] 0 bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 r txphyi x bit 8 r txsdqi x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r tcfpi x this register is used to indicate interrupts generated from blocks associated with the transmit utopia/pos-phy interfaces, fifo, and cell/frame processors. tcfpi: the rcfp interrupt event indication (tcfpi) transitions to logic 1 when a hardware interrupt event is sourced from tcfp block. this bit is cleared to logic 0 when the interrupt is cleared. txsdqi: the txsdq interrupt event indication (txsdqi) transitions to logic 1 when a hardware interrupt event is sourced from the receive system fifo txsdq block. this bit is cleared to logic 0 when the interrupt is cleared. txphyi: the rxphy interrupt event indication (txphyi) transitions to logic 1 when a hardware interrupt event is sourced from the transmit system utopia/pos-phy interface txphy block. this bit is cleared to logic 0 when the interrupt is cleared.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 111 inte[6]: the interrupt enable (inte[6]) bit controls the assertion of the interrupt (intb) output. when a logic 1 is written to inte[6], the tcfpi, txsdqi or txphyi pending interrupt will assert the interrupt (intb) output. when a logic 0 is written to inte[6], the tcfpi, txsdqi or txphyi pending interrupt will not assert the interrupt (intb) output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 112 register 000ah: s/uni-2488 master interrupt status #7 bit type function default bit 15 r/w inte[7] 0 bit 14 unused x bit 13 unused x bit 12 r crsti x bit 11 r t8te4i x bit 10 r t8te3i x bit 9 r t8te2i x bit 8 r t8te1i x bit 7 r txanalogi x bit 6 r rxanalogi x bit 5 r dll_tfclki x bit 4 r dll_rfclki x bit 3 r r8td4i x bit 2 r r8td3i x bit 1 r r8td2i x bit 0 r r8td1i x this register allows the source of an active interrupt to be identified down to the block level. further register accesses are required for the block in question to determine the cause of an active interrupt and to acknowledge the interrupt source. tsb1, tsb2 etc?..: the interrupt event indications transition to logic 1 when a hardware interrupt event is sourced from the corresponding block. the corresponding bit is cleared to logic 0 when the interrupt is cleared.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 113 register 000bh: unused bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 unused x this register is unused
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 114 register 000ch: aps input telecombus synchronization delay bit type function default bit 15 unused x bit 14 unused x bit 13 r/w aij0dly[13] 0 bit 12 r/w aij0dly[12] 0 bit 11 r/w aij0dly[11] 0 bit 10 r/w aij0dly[10] 0 bit 9 r/w aij0dly[9] 0 bit 8 r/w aij0dly[8] 0 bit 7 r/w aij0dly[7] 0 bit 6 r/w aij0dly[6] 0 bit 5 r/w aij0dly[5] 0 bit 4 r/w aij0dly[4] 0 bit 3 r/w aij0dly[3] 0 bit 2 r/w aij0dly[2] 0 bit 1 r/w aij0dly[1] 0 bit 0 r/w aij0dly[0] 0 this register controls the delay from the apsifp input signal to the time when the s/uni-2488 may safely process the j0 characters delivered by the aps input serial data links ( apsi+/-[4:1]). aij0dly[13:0]: the aps input transport frame delay bits (aij0fp[13:0]) controls the delay, in refclk cycles, inserted by the s/uni-2488 before processing the j0 characters delivered by the aps input serial data links (apsi+/-[4:1]). aij0dly is set such that after the specified delay, all active aps input links would have delivered the j0 character. the relationships of aij0fp, aij0dly[13:0] and the system configuration are described in the functional timing section. valid values of aij0dly[13:0] are 0000h to 25f7h.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 115 register 000dh: aps output telecombus synchronization delay bit type function default bit 15 unused x bit 14 unused x bit 13 r/w aoj0refdly[13] 0 bit 12 r/w aoj0refdly[12] 0 bit 11 r/w aoj0refdly[11] 0 bit 10 r/w aoj0refdly[10] 0 bit 9 r/w aoj0refdly[9] 0 bit 8 r/w aoj0refdly[8] 0 bit 7 r/w aoj0refdly[7] 0 bit 6 r/w aoj0refdly[6] 0 bit 5 r/w aoj0refdly[5] 0 bit 4 r/w aoj0refdly[4] 0 bit 3 r/w aoj0refdly[3] 0 bit 2 r/w aoj0refdly[2] 0 bit 1 r/w aoj0refdly[1] 0 bit 0 r/w aoj0refdly[0] 0 this register controls the delay from the apsifp input signal to the time when the s/uni-2488 produces the j0 pulse on the aps output serial data links (apso+/-[4:1]). aoj0refdly[13:0]: the aps output transport frame delay bits (aoj0refdly [13:0]) control the delay, in refclk cycles, inserted by the s/uni-2488 between receiving a reference j0 frame pulse on apsifp, and presenting the outgoing j0 character on apso+/-[4:1]. the relationships of apsifp, aoj0refdly [13:0] and the system configuration are described in the functional timing section. valid values of aoj0refdly [13:0] are 0000h to 25f7h.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 116 register 000eh: s/uni-2488 diagnostics bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 r/w tsvca_esdis 0 bit 4 r/w rsvca_esdis 0 bit 3 r/w tld_val 0 bit 2 r/w tsld_val 0 bit 1 r/w ds 0 bit 0 r/w dd 0 dd: the disable descrambling (dd) bit is used to disable sonet descrambling perfomed by the rrmp block. when set to a logic 1, sonet descrambling is disabled. when set to a logic 0, sonet descrambling is enabled. for normal operation, this bit should be set to a logic zero. ds: the disable scrambling (ds) bit is used to disable sonet scrambling perfomed by the trmp block. when set to a logic 1, sonet scrambling is disabled. when set to a logic 0, sonet scrambling is enabled. for normal operation, this bit should be set to a logic zero. tsld_val: the tsld value (tsld_val) bit is used to set the value optionally inserted into the section or line dcc in the transmit data stream as configured using the tslden bit in the trmp configuration register. when set to a logic 1, ones are inserted. when set to a logic 0, zeros are inserted.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 117 tld_val: the tld value (tld_val) bit is used to set the value optionally inserted into the section or line dcc in the transmit data stream as configured using the tlden bit in the trmp configuration register. when set to a logic 1, ones are inserted. when set to a logic 0, zeros are inserted. rsvca_esdis: the rsvca elastic store disable (rsvca_esdis) bit is used to disable the elastic store. this bit should normally be set to 0. tsvca_esdis: the tsvca elastic store disable (tsvca_esdis) bit is used to disable the elastic store. this bit should normally be set to 0.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 118 register 000fh: s/uni-2488 free register bit type function default bit 15 r/w free[15] 0 bit 14 r/w free[14] 0 bit 13 r/w free[13] 0 bit 12 r/w free[12] 0 bit 11 r/w free[11] 0 bit 10 r/w free10] 0 bit 9 r/w free[9] 0 bit 8 r/w free[8] 0 bit 7 r/w free[7] 0 bit 6 r/w free[6] 0 bit 5 r/w free[5] 0 bit 4 r/w free[4] 0 bit 3 r/w free[3] 0 bit 2 r/w free[2] 0 bit 1 r/w free[1] 0 bit 0 r/w free[0] 0 free[7:0]: the free[7:0] field may be freely modified by firmware.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 119 register 0010h: rx2488 analog interrupt control/status bit type function default bit 15 r prbs_sync_i 0 bit 14 r prbs_err_i 0 bit 13 r fifo_ovrf_i 0 bit 12 r fifo_undf_i 0 bit 11 r los_i 0 bit 10 r dool_i 0 bit 9 r rool_i 0 bit 8 unused x bit 7 unused x bit 6 r/w prbs_sync_en 0 bit 5 r/w prbs_err_en 0 bit 4 r/w fifo_ovrf_en 0 bit 3 r/w fifo_undf_en 0 bit 2 r/w los_en 0 bit 1 r/w dool_en 0 bit 0 r/w rool_en 0 the interrupt control/status register is provided at rcs_2488 read/write address 0100. rool_en: the reference out of lock enable bit connects the rool_i status bit to the ecbi_intb pin of the rcs_2488. when rool_en is set to logic one, an interrupt on the ecbi_intb is generated upon assertion of the rool_i register bit. when rool_en is set low, a change in the rool_i status does not generate an interrupt. dool_en: the data out of lock enable bit connects the dool_i status bit to the ecbi_intb pin of the rcs_2488. when dool_en is set to logic one, an interrupt on the ecbi_intb is generated upon assertion of the dool_i register bit. when dool_en is set low, a change in the dool_i status does not generate an interrupt. los_en: the loss of signal enable bit connects the los_i status bit to the ecbi_intb pin of the rcs_2488. when los_en is set to logic one, an interrupt on the ecbi_intb is generated upon assertion of the los_i register bit. when los_en is set low, a change in the los_i status does not generate an interrupt. fifo_undf_en: the fifo underflow enable bit connects the fifo_undf_i status bit to the ecbi_intb pin of the rcs_2488. when fifo_undf_en is set to logic one, an interrupt on the ecbi_intb
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 120 is generated upon assertion of the fifo_undf_i register bit. when fifo_undf_en is set low, a change in the fifo_undf_i status does not generate an interrupt. fifo_ovrf_en: the fifo overflow enable bit connects the fifo_ovrf_i status bit to the ecbi_intb pin of the rcs_2488. when fifo_ovrf_en is set to logic one, an interrupt on the ecbi_intb is generated upon assertion of the fifo_ovrf_i register bit. when fifo_ovrf_en is set low, a change in the fifo_ovrf_i status does not generate an interrupt. prbs_err_en: the prbs error enable bit connects the prbs_err_i status bit to the ecbi_intb pin of the rcs_2488. when prbs_err_en is set to logic one, an interrupt on the ecbi_intb is generated upon assertion of the prbs_err_i register bit. when prbs_err_en is set low, a change in the prbs_err_i status does not generate an interrupt. prbs_sync_en: the prbs synchronized enable bit connects the prbs_sync_i status bit to the ecbi_intb pin of the rcs_2488. when prbs_sync_en is set to logic one, an interrupt on the ecbi_intb is generated upon assertion of the prbs_sync_i register bit. when prbs_sync_en is set low, a change in the prbs_sync_i status does not generate an interrupt. rool_i: the recovered reference out of lock status indicates the clock recovery phase locked loop is unable to lock to the reference clock on refclk. rool_i is a logic one if the divided down synthesized clock frequency is not within 488 ppm of the refclk frequency. at startup, rool_i may remain at logic 1 for several hundred millisecond while the pll obtains lock. this bit is only cleared by over-writing with a ?1?. dool_i: the recovered data out of lock status indicates the clock recovery phase locked loop is unable to recover and lock to the input data stream. dool_i is a logic one if the divided down recovered clock frequency is not within 488 ppm of the refclk frequency of if no transitions have occurred on the rxd input for more than los_count[4:0] bits. this bit is only cleared by over-writing with a ?1?. los_i: the loss of signal status indicates the receive signal is lost or at least los_count[4:0] consecutive ones or zeros have been received. los_i is a logic zero if the sdi input is high or less than los_count[4:0] consecutive ones or zeros have been received. los_i is a logic one if the sdi input is low or los_count[4:0] consecutive ones or zeros have been received. this bit is only cleared by over-writing with a ?1?.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 121 fifo_undf_i: the fifo underflow bit provides a status indication of an underflow condition in the rx data slip-buffer. when fifo_undf_i is set to ?1? the data written to the slip-buffer has underflowed and data invalid data has been read from the fifo. this bit is only cleared by over-writing with a ?1?. fifo_ovrf_i: the fifo overflow bit provides a status indication of an overflow condition in the rx data slip-buffer. when fifo_ovrf_i is set to ?1? the data written to the slip-buffer has overflowed and data has been lost. this bit is only cleared by over-writing with a ?1?. prbs_err_i: the prbs bit error bit provides a status indication that a bit error has been detected in the comparison between the incoming data and the locally generated data. the prbs_err_i is set high when the monitor is in the synchronized state and when an error in a prbs byte is detected. this bit is only cleared by over-writing with a ?1?. prbs_sync_i: the prbs synchronization bit indicates that a change in the status of prbs monitor has occurred. the comparison between the incoming data and the prbs pattern generated locally. the prbs_sync_i is set high when the monitor is in the synchronized state and has received four consecutive errored bytes forcing the prbs monitor to resynchronize. this bit is only cleared by over-writing with a ?1?.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 122 register 0011h: rx2488 analog cru control bit type function default bit 15 unused x bit 14 r/w cru_reset 0 bit 13 r/w csu_reset 0 bit 12 r/w rx2488_enable 1 bit 11 r/w cru_enable 1 bit 10 unused x bit 9 r/w iddq_enable 0 bit 8 r/w csu_clock 0 bit 7 r/w cru_mode[7] 0 bit 6 r/w cru_mode[6] 0 bit 5 r/w cru_mode[5] 1 bit 4 r/w cru_mode[4] 0 bit 3 r/w cru_mode[3] 1 bit 2 r/w cru_mode[2] 0 bit 1 r/w cru_mode[1] 0 bit 0 r/w cru_mode[0] 1 the cru control register is provided at rcs_2488 read/write address 0101. cru_mode[7:0]: the cru mode control bits are used to place the cru is one of the following modes:
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 123 table 8 cru mode control mode bits description 7 override lock to data. when high forces the cru to remain locked to the reference clock. when low the cru state machine controls the cru. 6:5 loop filter modes: 00 = 1.25 k ohm 01 = 2.5 k ohm 10 = 5.0 k ohm 11 = 10 k ohm the default is 2.5 k ohm 4 disable narrow-banding feature (i.e. current offset). active high 3 enable csu narrow-banding and disable on- board ico current offset. active high 2 override lock to reference. when high forces the cru to remain locked to the data. when low the cru state machine controls the cru. 1:0 rate select bits: 00 = oc3 01 = oc48 10 = oc12 11 = oc48 csu_clock: the clock source unit reference clock selection bit is used to select the source of the csu clock. if csu_clock is set to logic 1 the clock for csuclki input pin is used as the reference. if csu_clock is set to logic 0 than the reference clock is obtained from the cru. iddq_enable: the iddq_enable bit activates the iddq (quiescent current) test mode. when set to ?1? all analog circuits are disabled and the iddq of the digital circuits can be measured. when this bit is set to ?0? all analog circuits operate normally. this bit is only used during production testing. cru_enable: the clock recovery unit enable provides a global power down of the cru analog block circuit. when set to ?0? this bit forces the abc to a low power state and functionality is disabled. when set to ?1? the abc operates in the normal mode of operation.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 124 rx2488_enable: the 2.488ghz receiver enable provides a global power down of the rx2488 analog block circuit. when set to ?0? this bit forces the abc to a low power state and functionality is disabled. when set to ?1? the abc operates in the normal mode of operation. csu_reset: the clock source unit reset provides a complete reset of the cru analog block circuit. when set to ?0? this bit forces the abc to a known initial state. while the bit is set to ?1? the functionality of the block is disabled. when set to ?0? the abc operates in the normal mode of operation. this bit is not self-clearing. therefore a ?0? must writing to the bit to remove the reset condition. cru_reset: the clock recovery unit reset provides a complete reset of the cru analog block circuit. when set to ?0? this bit forces the abc to a known initial state. while the bit is set to ?1? the functionality of the block is disabled. when set to ?0? the abc operates in the normal mode of operation. this bit is not self-clearing. therefore a ?0? must writing to the bit to remove the reset condition.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 125 register 0012h: rx2488 analog cru clock training configuration and status bit type function default bit 15 r/w los_count[4] 1 bit 14 r/w los_count[3] 0 bit 13 r/w los_count[2] 0 bit 12 r/w los_count[1] 0 bit 11 r/w los_count[0] 0 bit 10 r/w fill_level[5] 1 bit 9 r/w fill_level[4] 1 bit 8 r/w fill_level[3] 0 bit 7 r/w fill_level[2] 0 bit 6 r/w fill_level[1] 0 bit 5 r/w fill_level[0] 0 bit 4 r train 0 bit 3 r/w outlock 0 bit 2 r/w outdata 0 bit 1 r/w inlock 1 bit 0 r/w indata 1 the cru clock training configuration register is provided at rcs_2488 read/write address 2. indata: the clock difference detector data to lock transition configuration bit determines the number of times the clock difference detector must pass before the cru control state machine transitions from the locked to reference state to the data in range state. when indata is a logic zero, the clock difference detector must pass once before the state transition can occur. when indata is a logic one, the clock difference detector must pass 39 consecutive times before the state transition can occur. inlock: the clock difference detector locking to data transition configuration bit determines the number of times the clock difference detector must pass before the cru control state machine transitions from the data in range state to the locked to data state. when inlock is a logic zero, the clock difference detector must pass once before the state transition can occur. when inlock is a logic one, the clock difference detector must pass 39 consecutive times before the state transition can occur. outdata: the clock difference detector dropping out of lock transition configuration bit determines the number of times the clock difference detector must fail before the cru control state machine transitions from the data in range state to the locked to reference state. when outdata is a logic zero, the clock difference detector must fail once before the
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 126 state transition can take place. when outdata is a logic one, the clock difference detector must fail 39 consecutive times before the state transition can occur. outlock: the clock difference detector dropping out of data transition configuration bit determines the number of times the clock difference detector must pass before the cru control state machine transitions from the locked to data state to the data in range state. when outlock is a logic zero, the clock difference detector must fail once before the state transition can occur. when outlock is a logic one, the clock difference detector must fail 39 consecutive times before the state transition can occur. train: the cru reference training status indicates if the cru is locking to the reference clock or the locking to the receive data as described in tbd. train is a logic one if the cru is locking or locked to the reference clock. train is a logic zero if the cru is locking or locked to the receive data. train is invalid if the cru is not used. fill_level[3:0]: the fifo fill level sets the amount of data that must be accumulated in the fifo before valid data is output to the system. the level ensures that enough data is in the fifo to prevent an underflow condition caused by jitter on the input clock. the default value is set to 48 or one half of the fifo?s total capacity of 96 words. los_count[3:0]: the loss of signal 1?s/0?s transition detector count. this field sets the value for the number of consecutive all-zeros or all-ones pattern that will force the cru out of the lock to data state. each bit in the binary count represents 8 ones or zeros in the pattern. i.e. to set the consecutive all-ones or all-zeros pattern to 128 the los_count should be set to ?10000?b. the default value for this field is 128.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 127 register 0013h: rx2488 analog prbs control bit type function default bit 15 r prbs_err_cnt[7] 0 bit 14 r prbs_err_cnt[6] 0 bit 13 r prbs_err_cnt[5] 0 bit 12 r prbs_err_cnt[4] 0 bit 11 r prbs_err_cnt[3] 0 bit 10 r prbs_err_cnt[2] 0 bit 9 r prbs_err_cnt[1] 0 bit 8 r prbs_err_cnt[0] 0 bit 7 w latch_err_cnt x bit 6 unused x bit 5 r/w inv_data 0 bit 4 r/w fifo_clock 0 bit 3 r sync_stat 0 bit 2 r/w prbs_fpatt 0 bit 1 r/w prbs_enable 0 bit 0 r/w resync 0 the cru clock training configuration register is provided at rcs_2488 read/write address 3. resync: forces the monitor to re-initialize the prbs sequence. when set high, the monitor?s state machine will be forced in the out-of-sync state and automatically tries to resynchronize to the incoming stream. this bit is cleared once the monitor enters the in-sync state. prbs_enable: this bit enables the prbs monitor of the rcs_2488. when low, the prbs monitor is disabled. when high the prbs monitor is enabled and will check the incoming data stream for errors. prbs_fpatt: this bit determines whether the rcs_2488 is monitoring a prbs data stream or a fixed pattern. when low, the data stream contains prbs bytes, and when high the fixed pattern written into the pattern[15:0] register is monitored. sync_stat: the monitor synchronization status bit reflects the state of the monitor?s state machine. when sync_stat is set low, the monitor has lost synchronization. when sync_stat is high, the monitor is in synchronization.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 128 fifo_clock: the fifo clock source selection bit is used to select the source of the fifo output. if fifo_clock is set to logic 1 the clock for cru output clock is used as the reference. if fifo_clock is set to logic 0 than the fifo clock is obtained from the csu. inv_data: the serial data inversion inv_data controls the polarity of the received data. when inv_data is set to ?1? the polarity of the rxd+/- input pins invert. when inv_data is set to ?0? the rxd+/- inputs operate normally. latch_err_cnt: the latch error count bit loads the prbs byte error count value. when a logic 1 is written to this bit the prbs byte error count register is loaded into the latch_err_cnt[7:0] register and the prbs byte error count is reset to zero. this bit is write only and is cleared immediately after the write is complete. prbs_err_cnt[7:0]: the err_cnt[7:0] register, is the number of errors in the prbs bytes detected during the monitoring. errors are accumulated only when the monitor is in the synchronized state. even if there is multiple errors within one prbs byte, only one error is counted. the transfer of the error counter to this holding register is trigger by writing to the latch_err_cnt bit or by pulsing high the lclk signal. this prbs_err_cnt[7:0] is cleared after it is read. the actual prbs error counter is cleared immediately after a logic 1 is written to the latch_err_cnt bit. the error counter will not wrap around after reaching ffh, it will saturate to this value.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 129 register 0014h: rx2488 analog pattern register bit type function default bit 15 r/w fpatt[15] 0 bit 14 r/w fpatt[14] 0 bit 13 r/w fpatt[13] 0 bit 12 r/w fpatt[12] 0 bit 11 r/w fpatt[11] 0 bit 10 r/w fpatt[10] 0 bit 9 r/w fpatt[9] 0 bit 8 r/w fpatt[8] 0 bit 7 r/w fpatt[7] 0 bit 6 r/w fpatt[6] 0 bit 5 r/w fpatt[5] 0 bit 4 r/w fpatt[4] 0 bit 3 r/w fpatt[3] 0 bit 2 r/w fpatt[2] 0 bit 1 r/w fpatt[1] 0 bit 0 r/w fpatt[0] 0 the pattern register is provided at rcs_2488 read/write address 4. fpatt[15:0]: the fpatt[15:0] provides the fixed pattern that will be monitored for when the prbs_fpatt bit is set to a logic 1. if prbs_fpatt is set to logic 0 this register is not used.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 130 register 0030h: srli clock configuration bit type function default bit 15 r/w rotateen 1 bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 r/w disfrm4 0 bit 8 r/w disfrm3 0 bit 7 r/w disfrm2 0 bit 6 r/w disfrm1 0 bit 5 r/w disfrm 0 bit 4 r/w rclk4en 0 bit 3 r/w rclk3en 0 bit 2 r/w rclk2en 0 bit 1 r/w rclk1en 0 bit 0 unused the clock configuration register is provided at srli r/w address 0030h. rclk1en: the receive clock enable (rclk1en) bit controls the gating of the rclk1 output clock. when rclk1en is set to logic 1, the rclk1 output clock operates normally. when rclk1en is set to logic 0, the rclk1 output clock is held low. rclk2en: the receive clock enable (rclk2en) bit controls the gating of the rclk2 output clock. when rclk2en is set to logic 1, the rclk2 output clock operates normally. when rclk2en is set to logic 0, the rclk2 output clock is held low. rclk3en: the receive clock enable (rclk3en) bit controls the gating of the rclk3 output clock. when rclk3en is set to logic 1, the rclk3 output clock operates normally. when rclk3en is set to logic 0, the rclk3 output clock is held low.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 131 rclk4en: the receive clock enable (rclk4en) bit controls the gating of the rclk4 output clock. when rclk4en is set to logic 1, the rclk4 output clock operates normally. when rclk4en is set to logic 0, the rclk4 output clock is held low. disfrm: the disable framing (disfrm) bit disables the framing algorithm and resets the bit alignment on the rd[15:0] input bus to none. when disfrm is set to logic 1, the framing algorithm is disable and the bit alignment is reset to none. when disfrm is set to logic 0, the framing algorithm is enable and the bit alignment is done when out of frame is declared. disfrm1: the disable framing (disfrm1) bit disables the framing algorithm and resets the bit alignment on the rd1[7:0] input bus to none. when disfrm1 is set to logic 1, the framing algorithm is disable and the bit alignment is reset to none. when disfrm1 is set to logic 0, the framing algorithm is enable and the bit alignment is done when out of frame is declared. disfrm2: the disable framing (disfrm2) bit disables the framing algorithm and resets the bit alignment on the rd2[7:0] input bus to none. when disfrm2 is set to logic 1, the framing algorithm is disable and the bit alignment is reset to none. when disfrm2 is set to logic 0, the framing algorithm is enable and the bit alignment is done when out of frame is declared. disfrm3: the disable framing (disfrm3) bit disables the framing algorithm and resets the bit alignment on the rd3[7:0] input bus to none. when disfrm3 is set to logic 1, the framing algorithm is disable and the bit alignment is reset to none. when disfrm3 is set to logic 0, the framing algorithm is enable and the bit alignment is done when out of frame is declared. disfrm4: the disable framing (disfrm4) bit disables the framing algorithm and resets the bit alignment on the rd4[7:0] input bus to none. when disfrm4 is set to logic 1, the framing algorithm is disable and the bit alignment is reset to none. when disfrm4 is set to logic 0, the framing algorithm is enable and the bit alignment is done when out of frame is declared. rotateen: the tsi rotate enable (rotateen) bit controls the tsi rotation matrix. when rotateen is set to logic 1, the tsi rotation matrix is active and the bytes on the rd[15:0] output bus are re ordered. when rotateen is set to logic 0, the tsi rotation matrix is inactive.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 132 register 0031h: srli pgm clock configuration bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 unused bit 5 unused bit 4 unused bit 3 r/w pgmrclksrc[1] 0 bit 2 r/w pgmrclksrc[0] 0 bit 1 r/w pgmrclksel 0 bit 0 r/w pgmrclken 0 the pgm clock configuration register is provided at srli r/w address 0031h. pgmrclken: the programmable receive clock enable (pgmrclken) bit controls the gating of the pgmrclk output clock. when pgmrclken is set to logic one, the pgmrclk output clock operates normally. when pgmrclken is set to logic zero, the pgmrclk output clock is held low. pgmrclksel the programmable receive clock frequency selection (pgmrclksel) bit selects the frequency of the pgmrclk output clock. when pgmrclksel is set high, pgmrclk is a nominal 8 khz clock. when pgmrclksel is set to logic zero, pgmrclk is a nominal 19.44 mhz clock.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 133 pgmrclksrc[1:0]: the programmable receive clock source (pgmrclksrc[1:0]) bits select the source of the pgmrclk output clock when the s/uni-2488 is in quad sts-12 (stm-4) mode. when the sp2488 is in sts-48 (stm-16) mode, rdclk is the source of the pgmrclk output clock. pgmrclksrc[1:0] source 00 piclk1 01 piclk2 10 piclk3 11 piclk4
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 134 register 0038h: stli clock configuration bit type function default bit 15 r/w reserved 0 bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 unused bit 5 unused bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w tdclkoen 0 tdclkoen: the transmit clock enable (tdclkoen) bit controls the gating of the internal parallel transmit clock. when tdclkoen is set to logic 1, the tdclko output clock operates normally. when tdclkoen is set to logic 0, the tdclko output clock is held low. this register bit should be set to loic 1 for normal operation.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 135 register 0039h: stli pgm clock configuration bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 unused bit 5 unused bit 4 unused bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w pgmtclksel 0 bit 0 r/w pgmtclken 0 pgmtclken: the programmable transmit clock enable (pgmtclken) bit controls the gating of the pgmtclk output clock. when pgmtclken is set to logic one, the pgmtclk output clock operates normally. when pgmtclken is set to logic zero, the pgmtclk output clock is held low. pgmtclksel
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 136 the programmable transmit clock frequency selection (pgmtclksel) bit selects the frequency of the pgmtclk output clock. when pgmtclksel is set high, pgmtclk is a nominal 8 khz clock. when pgmtclksel is set to logic zero, pgmtclk is a nominal register 0040h: rrmp configuration bit type function default bit 15 r busy x bit 14 unused bit 13 unused bit 12 r/w lreiblk 0 bit 11 r/w reserved 0 bit 10 r/w reserved 0 bit 9 r/w lbipeaccblk 0 bit 8 r/w reserved 0 bit 7 r/w sbipeaccblk 0 bit 6 r/w reserved 1 bit 5 r/w reserved 0 bit 4 r/w reserved 1 bit 3 r/w lrdi3 0 bit 2 r/w lais3 0 bit 1 r/w algo2 0 bit 0 w foof x foof: the force out of frame (foof) bit forces out of frame condition. when a logic 1 is written to foof, the framer block is forced out of frame at the next frame boundary regardless of the framing pattern value. the oof event initiates re framing in an upstream frame detector. algo2: the algo2 bit selects the framing pattern used to determine and maintain the frame alignment. when algo2 is set to logic 1, the framing pattern consist of the 8 bits of the first a1 framing bytes and the first 4 bits of the last a2 framing bytes (12 bits total). this algorithm examines only 12 framing bits; all other framing bits are ignored. when algo2 is set to logic 0, the framing patterns consist of 12 a1 framing bytes and 12 a2 framing bytes. lais3: the line alarm indication signal detection (lais3) bit selects the line ais detection algorithm. when lais3 is set to logic 1, line ais is declared when a 111 pattern is detected in bits 6,7,8 of the k2 byte for three consecutive frames. when lais3 is set to logic 0, line ais is
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 137 declared when a 111 pattern is detected in bits 6,7,8 of the k2 byte for five consecutive frames. lrdi3: the line remote defect indication detection (lrdi3) bit selects the line rdi detection algorithm. when lrdi3 is set to logic 1, line rdi is declared when a 110 pattern is detected in bits 6,7,8 of the k2 byte for three consecutive frames. when lrdi3 is set to logic 0, line rdi is declared when a 110 pattern is detected in bits 6,7,8 of the k2 byte for five consecutive frames. sbipeaccblk: the section bip error accumulation block (sbipeaccblk) bit controls the accumulation of section bip errors. when sbipeaccblk is set to logic 1, the section bip accumulation represents bip-8 block errors (a maximum of 1 error per frame). when sbipeaccblk is set to logic 0, the section bip accumulation represents bip-8 errors (a maximum of 8 errors per frame). lbipeaccblk: the line bip error accumulation block (lbipeaccblk) bit controls the accumulation of line bip errors. when lbipeaccblk is set to logic 1, the line bip accumulation represents bip- 24 block errors (a maximum of 1 error per sts-3/stm-1 per frame). when lbipeaccblk is set to logic 0, the line bip accumulation represents bip-8 errors (a maximum of 8 errors per sts-1/stm-0 per frame). lreiblk the line rei block (lreiblk) bit controls the extraction of line rei errors from the m1 byte. when lreiblk is set to logic 1, the extracted line rei are interpreted as block bip-24 errors (a maximum of 1 error per sts-3/stm-1 per frame). when lreiblk is set to logic 0, the extracted line rei are interpreted as bip-8 errors (a maximum of 8 errors per sts-1/stm-0 per frame). busy: the busy (busy) bit reports the status of the transfer of section bip, line bip and line rei error counters to the holding registers. busy is set to logic 1 upon writing to the holding register addresses or by a low to high transition on lck. busy is set to logic 0, upon completion of the transfer. this bit should be polled to determine when new data is available in the holding registers.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 138 register 0041h: rrmp status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 unused bit 5 r apsbfv x bit 4 r lrdiv x bit 3 r laisv x bit 2 r losv x bit 1 r lofv x bit 0 r oofv x oofv: the oofv bit reflects the current status of the out of frame defect. the oof defect is declared when four consecutive frames have one or more bit error in their framing pattern. the oof defect is cleared when two error free framing pattern are found. lofv: the lofv bit reflects the current status of the loss of frame defect. the lof defect is declared when an out of frame condition exists for a total period of 3 ms during which there is no continuous in frame period of 3 ms. the lof defect is cleared when an in frame condition exists for a continuous period of 3 ms. losv: the losv bit reflects the current status of the loss of signal defect. the los defect is declared when 20 s of consecutive all zeros pattern is detected. the los defect is cleared when two consecutive error free framing patterns are found and during the intervening time (one frame) there is no violating period of consecutive all zeros pattern.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 139 laisv: the laisv bit reflects the current status of the line alarm indication signal defect. the ais-l defect is declared when the 111 pattern is detected in bits 6,7 and 8 of the k2 byte for three or five consecutive frames. the ais-l defect is cleared when any pattern other than 111 is detected in bits 6, 7, and 8 of the k2 byte for three or five consecutive frames. lrdiv: the lrdiv bit reflects the current status of the line remote defect indication signal defect. the rdi-l defect is declared when the 110 pattern is detected in bits 6, 7, and 8 of the k2 byte for three or five consecutive frames. the rdi-l defect is cleared when any pattern other than 110 is detected in bits 6, 7, and 8 of the k2 byte for three or five consecutive frames. apsbfv: the apsbf bit reflects the current status of the aps byte failure defect. the aps byte failure defect is declared when no three consecutive identical k1 bytes are received in the last twelve consecutive frames starting with the last frame containing a previously consistent byte. the aps byte failure defect is cleared when three consecutive identical k1 bytes are received.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 140 register 0042h: rrmp interrupt enable bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 r/w lreiee 0 bit 9 r/w lbipee 0 bit 8 r/w sbipee 0 bit 7 r/w cossme 0 bit 6 r/w coapse 0 bit 5 r/w apsbfe 0 bit 4 r/w lrdie 0 bit 3 r/w laise 0 bit 2 r/w lose 0 bit 1 r/w lofe 0 bit 0 r/w oofe 0 oofe, lofe, lose, laise, lrdie, apsbfe, coapse, cossme, sbipee, lbipee, lreiee: the interrupt enable bits controls the activation of the interrupt (intb) output. when the interrupt enable bit is set to logic 1, the corresponding pending interrupt will assert the interrupt (intb) output. when the interrupt enable bit is set to logic 0, the corresponding pending interrupt will not assert the interrupt (intb) output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 141 register 0043h: rrmp interrupt status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 r lreiei x bit 9 r lbipei x bit 8 r sbipei x bit 7 r commsi x bit 6 r coapsi x bit 5 r apsbfi x bit 4 r lrdii x bit 3 r laisi x bit 2 r losi x bit 1 r lofi x bit 0 r oofi x oofi: the out of frame interrupt status (oofi) bit is an event indicator. oofi is set to logic 1 to indicate any change in the status of oofv. the interrupt status bit is independent of the interrupt enable bit. oofi is cleared to logic 0 when this register is read. lofi: the loss of frame interrupt status (lofi) bit is an event indicator. lofi is set to logic 1 to indicate any change in the status of lofv. the interrupt status bit is independent of the interrupt enable bit. lofi is cleared to logic 0 when this register is read. losi: the loss of signal interrupt status (losi) bit is an event indicator. losi is set to logic 1 to indicate any change in the status of losv. the interrupt status bit is independent of the interrupt enable bit. losi is cleared to logic 0 when this register is read. laisi: the line alarm indication signal interrupt status (laisi) bit is an event indicator. laisi is set to logic 1 to indicate any change in the status of laisv. the interrupt status bit is independent of the interrupt enable bit. laisi is cleared to logic 0 when this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 142 lrdii: the line remote defect indication interrupt status (lrdii) bit is an event indicator. lrdii is set to logic 1 to indicate any change in the status of lrdiv. the interrupt status bit is independent of the interrupt enable bit. lrdii is cleared to logic 0 when this register is read. apsbfi: the aps byte failure interrupt status (apsbfi) bit is an event indicator. apsbfi is set to logic 1 to indicate any change in the status of apsbfv. the interrupt status bit is independent of the interrupt enable bit. apsbfi is cleared to logic 0 when this register is read. coapsi: the change of aps bytes interrupt status (coapsi) bit is an event indicator. coapsi is set to logic 1 to indicate a new aps bytes. the interrupt status bit is independent of the interrupt enable bit. coapsi is cleared to logic 0 when this register is read. cossmi: the change of ssm message interrupt status (cossmi) bit is an event indicator. cossmi is set to logic 1 to indicate a new ssm message. the interrupt status bit is independent of the interrupt enable bit. cossmi is cleared to logic 0 when this register is read. sbipei: the section bip error interrupt status (sbipei) bit is an event indicator. sbipei is set to logic 1 to indicate a section bip error. the interrupt status bit is independent of the interrupt enable bit. sbipei is cleared to logic 0 when this register is read. lbipei: the line bip error interrupt status (lbipei) bit is an event indicator. lbipei is set to logic 1 to indicate a line bip error. the interrupt status bit is independent of the interrupt enable bit. lbipei is cleared to logic 0 when this register is read. lreiei: the line rei error interrupt status (lreiei) bit is an event indicator. lreiei is set to logic 1 to indicate a line rei error. the interrupt status bit is independent of the interrupt enable bit. lreiei is cleared to logic 0 when this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 143 register 0044h: rrmp receive aps bit type function default bit 15 r k1v[7] x bit 14 r k1v[6] x bit 13 r k1v[5] x bit 12 r k1v[4] x bit 11 r k1v[3] x bit 10 r k1v[2] x bit 9 r k1v[1] x bit 8 r k1v[0] x bit 7 r k2v[7] x bit 6 r k2v[6] x bit 5 r k2v[5] x bit 4 r k2v[4] x bit 3 r k2v[3] x bit 2 r k2v[2] x bit 1 r k2v[1] x bit 0 r k2v[0] x k1v[7:0]/k2v[7:0]: the aps k1/k2 bytes value (k1v[7:0]/k2v[7:0]) bits represent the extracted k1/k2 aps bytes. k1v/k2v is updated when the same k1 and k2 bytes (forming a single entity) are received for three consecutive frames.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 144 register 0045h: rrmp receive ssm bit type function default bit 15 r/w bytessm 0 bit 14 r/w fltrssm 0 bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 r ssmv[7] x bit 6 r ssmv[6] x bit 5 r ssmv[5] x bit 4 r ssmv[4] x bit 3 r ssmv[3] x bit 2 r ssmv[2] x bit 1 r ssmv[1] x bit 0 r ssmv[0] x ssmv[7:0]: the synchronization status message value (ssmv[7:0]) bits represent the extracted s1 nibble (or byte). when filtering is enabled via the fltrssm register bit, ssmv is updated when the same s1 nibble (or byte) is received for eight consecutive frames. when filtering is disable, ssmv is updated every frame. fltrssm: the filter synchronization status message (fltrssm) bit enables the filtering of the ssm nibble (or byte). when fltrssm is set to logic 1, the ssm value is updated when the same ssm is received for eight consecutive frames. when fltrssm is set to logic 0, the ssm value is updated every frame. bytessm: the byte synchronization status message (bytessm) bit extends the ssm from a nibble to a byte. when bytessm is set to logic 1, the ssm is a byte and bits 1 to 8 of the s1 byte are considered. when bytessm is set to logic 0, the ssm is a nibble and only bits 5 to 8 of the s1 byte are considered.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 145 register 0046h: rrmp ais enable bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 unused bit 5 unused bit 4 r/w k2ais 0 bit 3 r/w rlaisins 0 bit 2 r/w rlaisen 0 bit 1 r/w rlohaisen 0 bit 0 r/w rsohaisen 0 rsohaisen: the receive section overhead ais enable (rsohaisen) bit enables ais insertion on rtoh when carrying section overhead bytes. when rsohaisen is set to logic 1, all ones are forced on the section overhead bytes when a lof or los condition exists. when rsohaisen is set to logic 0, no ais are forced on the section overhead bytes regardless of the alarm condition. this bit should be set to logic 1 for normal operation. rlohaisen: the receive line overhead ais enable (rlohaisen) bit enables ais insertion on rtoh, when carrying line overhead bytes. when rlohaisen is set to logic 1, all ones are forced on the line overhead bytes when a lof or los condition exists. when rlohaisen is set to logic 0, no ais are forced on the line overhead bytes regardless of the alarm condition. this bit should be set to logic 1 for normal operation.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 146 rlaisen: the receive line ais enable (rlaisen) bit enables line ais insertion in the outgoing data stream. when rlaisen is set to logic 1, line ais is inserted in the outgoing data stream when a lof or los condition exists. when rlaisen is set to logic 0, no line ais is inserted regardless of the alarm condition. this bit should be set to logic 1 for normal operation. rlaisins: the receive line ais insertion (rlaisin) bit forces line ais insertion in the receive sonet data stream. when rlaisins is set to logic 1, all ones are inserted in the line overhead bytes and in the payload bytes (all the bytes of the frame except the section overhead bytes) to force a line ais condition. when rlaisins is set to logic 0, the line ais condition is removed. k2ais: the k2 line ais (k2ais) bit restricts line ais to the k2 byte. when k2ais is set to logic 1, line ais is only inserted in bits 6, 7 and 8 of the k2 byte. when k2ais is set to logic 0, line ais is inserted in the line overhead bytes and in the payload bytes (all the bytes of the frame except the section overhead bytes).
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 147 register 0047h: rrmp section bip error counter bit type function default bit 15 r sbipe[15] x bit 14 r sbipe[14] x bit 13 r sbipe[13] x bit 12 r sbipe[12] x bit 11 r sbipe[11] x bit 10 r sbipe[10] x bit 9 r sbipe[9] x bit 8 r sbipe[8] x bit 7 r sbipe[7] x bit 6 r sbipe[6] x bit 5 r sbipe[5] x bit 4 r sbipe[4] x bit 3 r sbipe[3] x bit 2 r sbipe[2] x bit 1 r sbipe[1] x bit 0 r sbipe[0] x sbipe[15:0]: the section bip error (sbipe[15:0]) bits represent the number of section bip errors that have been detected since the last accumulation interval. the error counter is transferred to the holding registers by a microprocessor write to any of the rrmp counter registers or the s/uni-2488 identity, and global performance monitor update register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 148 register 0048h: rrmp line bip error counter (lsb) bit type function default bit 15 to bit 0 r lbipe[15:0] xxxx register 0049h: rrmp line bip error counter (msb) bit type function default bit 15 to bit 8 unused bit 7 to bit 0 r lbipe[23:16] xx lbipe[23:0]: the line bip error (lbipe[23:0]) bits represent the number of line bip errors that have been detected since the last accumulation interval. the error counter is transferred to the holding registers by a microprocessor write to any of the rrmp counter registers or the s/uni-2488 identity, and global performance monitor update register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 149 register 004ah: rrmp line rei error counter (lsb) bit type function default bit 15 to bit 0 r lreie[15:0] xxxx register 004bh: rrmp line rei error counter (msb) bit type function default bit 15 to bit 8 unused bit 7 to bit 0 rlreie[23:16]xx lreie[23:0]: the line rei error (lreie[23:0]) bits represent the number of line rei errors that have been detected since the last accumulation interval. the error counter is transferred to the holding registers by a microprocessor write to any of the rrmp counter registers or the s/uni-2488 identity, and global performance monitor update register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 150 register 0080h: trmp configuration bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r/w lreiblk 0 bit 10 r/w lreien 1 bit 9 r/w apsen 1 bit 8 r/w reserved 1 bit 7 r/w tlden 1 bit 6 r/w reserved 0 bit 5 r/w reserved 1 bit 4 r/w tslden 1 bit 3 r/w traceen 1 bit 2 r/w j0z0incen 0 bit 1 r/w z0def 0 bit 0 r/w a1a2en 1 a1a2en: the a1a2 framing enable (a1a2en) bit controls the insertion of the framing bytes in the data stream. when a1a2en is set to logic 1, f6h and 28h are inserted in the a1 and a2 bytes according to the priority of table 4. when a1a2en is set to logic 0, the framing bytes are not inserted. for normal operation, the a1a2en bits in the trmp aux1 configuration register, the trmp aux2 configuration register and the trmp aux3 configuration register must be set to the same value as the a1a2en bit. z0def: the z0 definition (z0def) bit defines the z0 growth bytes. when z0def is set to logic 1, the z0 bytes are defined according to itu. the z0 bytes are located in sts-1/stm-0 #2 to #12. when z0def is set to logic 0, the z0 bytes are defined according to bellcore. the z0 bytes are located in sts-1/stm-0 #2 to #48. for normal operation, the z0def bits in the trmp aux1 configuration register, the trmp aux2 configuration register and the trmp aux3 configuration register must be set to the same value as the z0def bit.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 151 j0z0incen: the j0 and z0 increment enable (j0z0incen) bit controls the insertion of an incremental pattern in the section trace and z0 growth bytes. when j0zoincen is set to logic 1, the corresponding sts-1/stm-0 path # is inserted in the j0 and z0 bytes according to the priority of table 4. when j0z0incen is set to logic 0, no incremental pattern is inserted. for normal operation, the j0z0incen bits in the trmp aux1 configuration register, the trmp aux2 configuration register and the trmp aux3 configuration register must be set to the same value as the j0z0incen bit. traceen: the section trace enable (traceen) bit controls the insertion of section trace in the data stream. when traceen is set to logic 1, the section trace from the section tttp block is inserted in the j0 byte of sts-1/stm-0 #1 according to the priority of table 4. when traceen is set to logic 0, the section trace from the j0[7:0] input port is not inserted. tslden: the tsld enable (tslden) bit controls the insertion of section or line dcc in the data stream. when tslden is set to logic 1, the s/uni-2488 inserts all ones or all zeros as selected using the tsld_val bit in the s/uni-2488 diagnostic register into the d1-d3 bytes or d4-d12 bytes of sts-1/stm-0 #1 according to the priority of table 4. when tslden is set to logic 0, the section or line dcc is not inserted. tlden: the tld enable (tlden) bit controls the insertion of line dcc in the data stream. when tlden is set to logic 1, the s/uni-2488 inserts all ones or all zeros as selected using the tld_val bit in the s/uni-2488 diagnostic register into in the d4-d12 bytes of sts-1/stm-0 #1 according to the priority of table 4. when tlden is set to logic 0, an all ones pattern is not inserted. apsen: the aps enable (apsen) bit controls the insertion of automatic protection switching in the data stream. when apsen is set to logic 1, the aps bytes from the rrmp are inserted in the k1/k2 bytes of sts-1/stm-0 #1 according to the priority of table 4. when apsen is set to logic 0, the aps bytes from the rrmp are not inserted. lreien: the line rei enable (lreien) bit controls the insertion of line remote error indication in the data stream. when lreien is set to logic 1, the line rei from the rrmp is inserted in the m1 byte of sts-1/stm-0 #3 according to the priority of table 4. when lreien is set to logic 0, the line rei from the rrmp is not inserted.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 152 lreiblk: the line rei block error (lreiblk) bit controls the generation of line remote error indication. when lreiblk is set to logic 1, the line rei inserted in the m1 byte represents bip-24 block errors (a maximum of 1 error per sts-3/stm-1 per frame). when lreiblk is set to logic 0, the line rei inserted in the m1 byte represents bip-8 errors (a maximum of 8 error per sts- 1/stm-0 per frame).
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 153 register 0081h: trmp register insertion bit type function default bit 15 r/w unusedv 0 bit 14 r/w unuseden 0 bit 13 r/w nationalv 0 bit 12 r/w nationalen 0 bit 11 unused bit 10 r/w e2regen 0 bit 9 r/w z2regen 0 bit 8 r/w z1regen 0 bit 7 r/w s1regen 0 bit 6 r/w d4d12regen 0 bit 5 r/w k1k2regen 0 bit 4 r/w d1d3regen 0 bit 3 r/w f1regen 0 bit 2 r/w e1regen 0 bit 1 r/w z0regen 0 bit 0 r/w j0regen 0 j0regen: the j0 register enable (j0regen) bit controls the insertion of section trace in the data stream. when j0regen is set to logic 1, the section trace from the trmp transmit j0 and z0 register is inserted in the j0 byte of sts-1/stm-0 #1 according to the priority of table 4. when j0regen is set to logic 0, the section trace from the trmp transmit j0 and z0 register is not inserted. z0regen: the z0 register enable (z0regen) bit controls the insertion of z0 growth bytes in the data stream. when z0regen is set to logic 1, the z0 growth byte from the trmp transmit j0 and z0 register is inserted in the z0 bytes according to the priority of table 4. when z0regen is set to logic 0, the z0 growth byte from the trmp transmit j0 and z0 register is not inserted. the z0def bit in the trmp configuration register bit defines the z0 bytes. e1regen: the e1 register enable (e1regen) bit controls the insertion of section order wire in the data stream. when e1regen is set to logic 1, the section order wire from the trmp transmit e1 and f1 register is inserted in the e1 byte of sts-1/stm-0 #1 according to the priority of table 4. when e1regen is set to logic 0, the section order wire from the trmp transmit e1 and f1 register is not inserted.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 154 f1regen: the f1 register enable (f1regen) bit controls the insertion of section user channel in the data stream. when f1regen is set to logic 1, the section user channel from the trmp transmit e1 and f1 register is inserted in the f1 byte of sts-1/stm-0 #1 according to the priority of table 4. when f1regen is set to logic 0, the section user channel from the trmp transmit e1 and f1 register is not inserted. d1d3regen: the d1 to d3 register enable (d1d3regen) bit controls the insertion of section data communication channel in the data stream. when d1d3regen is set to logic 1, the section dcc from the trmp transmit d1d3 and d4d12 register is inserted in the d1 to d3 bytes of sts-1/stm-0 #1 according to the priority of table 4. when d1d3regen is set to logic 0, the section dcc from the trmp transmit d1d3 and d4d12 register is not inserted. k1k2regen: the k1k2 register enable (k1k2regen) bit controls the insertion of automatic protection switching in the data stream. when k1k2regen is set to logic 1, the aps bytes from the trmp transmit k1 and k2 register are inserted in the k1, k2 bytes of sts-1/stm-0 #1 according to the priority of table 4. when k1k2regen is set to logic 0, the aps bytes from the trmp transmit k1 and k2 register are not inserted. d4d12regen: the d4 to d12 register enable (d4d12regen) bit controls the insertion of line data communication channel in the data stream. when d4d12regen is set to logic 1, the line dcc from the trmp transmit d1d3 and d4d12 register is inserted in the d4 to d12 bytes of sts-1/stm-0 #1 according to the priority of table 4. when d4d12regen is set to logic 0, the line dcc from the trmp transmit d1d3 and d4d12 register is not inserted. s1regen: the s1 register enable (s1regen) bit controls the insertion of the synchronization status message in the data stream. when s1regen is set to logic 1, the ssm from the trmp transmit s1 and z1 register is inserted in the s1 byte of sts-1/stm-0 #1 according to the priority of table 4. when s1regen is set to logic 0, the ssm from the trmp transmit s1 and z1 register is not inserted. z1regen: the z1 register enable (z1regen) bit controls the insertion of z1 growth bytes in the data stream. when z1regen is set to logic 1, the z1 byte from the trmp transmit s1 and z1 register is inserted in the z1 bytes according to the priority of table 4. when z1regen is set to logic 0, the z1 byte from the trmp transmit s1 and z1 register is not inserted.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 155 z2regen: the z2 register enable (z2regen) bit controls the insertion of z2 growth bytes in the data stream. when z2regen is set to logic 1, the z2 byte from the trmp transmit z2 and e2 register is inserted in the z2 bytes according to the priority of table 4. when z2regen is set to logic 0, the z2 byte from the trmp transmit z2 and e2 register is not inserted. e2regen: the e2 register enable (e2regen) bit controls the insertion of line order wire in the data stream. when e2regen is set to logic 1, the line order wire from the trmp transmit z2 and e2 register is inserted in the e2 byte of sts-1/stm-0 #1 according to the priority of table 4. when e2regen is set to logic 0, the line order wire from the trmp transmit z2 and e2 register is not inserted. nationalen: the national enable (nationalen) bit controls the insertion of national bytes in the data stream. when nationalen is set to logic 1, an all one or an all zero pattern is inserted in the national bytes according to the priority of table 4. when nationalen is set to logic 0, no pattern is inserted. the z0def bit in the trmp configuration register defines the national bytes of row #1. nationalv: the national value (nationalv) bit controls the value inserted in the national bytes. when nationalv is set to logic 1, an all one pattern is inserted in the national bytes if enable via the nationalen register bit. when nationalv is set to logic 0, an all zero pattern is inserted in the national bytes if enable via the nationalen register bit. unuseden: the unused enable (unuseden) bit controls the insertion of unused bytes in the data stream. when unuseden is set to logic 1, an all one or an all zero pattern is inserted in the unused bytes according to the priority of table 4. when unuseden is set to logic 0, no pattern is inserted. unusedv: the unused value (unusedv) bit controls the value inserted in the unused bytes. when unusedv is set to logic 1, an all one pattern is inserted in the unused bytes if enable via the unuseden register bit. when unusedv is set to logic 0, an all zero pattern is inserted in the unused bytes if enable via the unuseden register bit.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 156 register 0082h: trmp error insertion bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 r/w losins 0 bit 5 r/w laisins 0 bit 4 r/w lrdiins 0 bit 3 r/w a1err 0 bit 2 r/w hmasken 1 bit 1 r/w b2masken 1 bit 0 r/w b1masken 1 b1masken: the b1 mask enable (b1masken) bit selects the used of the b1 byte extracted from the ttoh port. when b1masken is set to logic 1, the b1 byte extracted from the ttoh port is used as a mask to toggle bits in the calculated b1 byte (the b1 byte extracted from the ttoh port is xor with the calculated b1 byte). when b1masken is set to logic 0, the b1 byte extracted from the ttoh port is inserted instead of the calculated b1 byte. b2masken: the b2 mask enable (b2masken) bit selects the used of the b2 bytes extracted from the ttoh port. when b2masken is set to logic 1, the b2 bytes extracted from the ttoh port are used as a mask to toggle bits in the calculated b2 bytes (the b2 bytes extracted from the ttoh port are xor with the calculated b2 bytes). when b2masken is set to logic 0, the b2 bytes extracted from the ttoh port are inserted instead of the calculated b2 bytes. hmasken: the h1/h2 mask enable (hmasken) bit selects the used of the h1/h2 bytes extracted from the ttoh port. when hmasken is set to logic 1, the h1/h2 bytes extracted from the ttoh port are used as a mask to toggle bits in the h1/h2 path payload pointer bytes (the h1/h2 bytes extracted from the ttoh port are xor with the path payload pointer bytes). when
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 157 hmasken is set to logic 0, the h1/h2 bytes extracted from the ttoh port are inserted instead of the path payload pointer bytes. a1err: the a1 error insertion (a1err) bit is used to introduce framing errors in the a1 bytes. when a1err is set to logic 1, 76h instead of f6h is inserted in all of the a1 bytes of the sts- 12/stm-4 #1 according to the priority of table 4. when a1err is set to logic 0, no framing errors are introduced. lrdiins: the line rdi insertion (lrdiins) bit is used to force a line remote defect indication in the data stream. when lrdiins is set to logic 1, the 110 pattern is inserted in bits 6, 7 and 8 of the k2 byte of sts-1/stm-0 #1 to force a line rdi condition. when lrdiins is set to logic 0, the line rdi condition is removed. laisins: the line ais insertion (laisins) bit is used to force a line alarm indication signal in the data stream. when laisins is set to logic 1, all ones are inserted in the line overhead and in the payload (all the bytes of the frame except the section overhead bytes) to force a line ais condition. when laisins is set to logic 0, the line ais condition is removed. line ais is inserted/removed on frame boundary before scrambling. note, this bit must be set to the same value as the other laisins bits in the trmp aux2 error insertion, trmp aux3 error insertion and trmp aux4 error insertion registers. losins: the los insertion (losins) bit is used to force a loss of signal condition in the data stream. when losins is set to logic 1, the data steam is set to all zero (after scrambling) to force a loss of signal condition. when losins is set to logic 0, the loss of signal condition is removed. note, this bit must be set to the same value as the other losins bits in the trmp aux2 error insertion, trmp aux3 error insertion and trmp aux4 error insertion registers.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 158 register 0083h: trmp transmit j0 and z0 bit type function default bit 15 r/w j0v[7] 0 bit 14 r/w j0v[6] 0 bit 13 r/w j0v[5] 0 bit 12 r/w j0v[4] 0 bit 11 r/w j0v[3] 0 bit 10 r/w j0v[2] 0 bit 9 r/w j0v[1] 0 bit 8 r/w j0v[0] 0 bit 7 r/w z0v[7] 0 bit 6 r/w z0v[6] 0 bit 5 r/w z0v[5] 0 bit 4 r/w z0v[4] 0 bit 3 r/w z0v[3] 0 bit 2 r/w z0v[2] 0 bit 1 r/w z0v[1] 0 bit 0 r/w z0v[0] 0 z0v[7:0]: the z0 byte value (z0v[7:0]) bits hold the z0 growth byte to be inserted in the data stream. the z0v[7:0] value is inserted in the z0 bytes if the insertion is enabled via the z0regen bit in the trmp register insertion register. the z0def bit in the trmp configuration register defines the z0 bytes. j0v[7:0]: the j0 byte value (j0v[7:0]) bits hold the section trace to be inserted in the data stream. the j0v[7:0] value is inserted in the j0 byte of sts-1/stm-0 #1 if the insertion is enabled via the j0regen bit in the trmp register insertion register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 159 register 0084h: trmp transmit e1 and f1 bit type function default bit 15 r/w e1v[7] 0 bit 14 r/w e1v[6] 0 bit 13 r/w e1v[5] 0 bit 12 r/w e1v[4] 0 bit 11 r/w e1v[3] 0 bit 10 r/w e1v[2] 0 bit 9 r/w e1v[1] 0 bit 8 r/w e1v[0] 0 bit 7 r/w f1v[7] 0 bit 6 r/w f1v[6] 0 bit 5 r/w f1v[5] 0 bit 4 r/w f1v[4] 0 bit 3 r/w f1v[3] 0 bit 2 r/w f1v[2] 0 bit 1 r/w f1v[1] 0 bit 0 r/w f1v[0] 0 f1v[7:0]: the f1 byte value (f1v[7:0]) bits hold the section user channel to be inserted in the data stream. the f1v[7:0] value is inserted in the f1 byte of sts-1/stm-0 #1 if the insertion is enabled via the f1regen bit in the trmp register insertion register. e1v[7:0]: the e1 byte value (e1v[7:0]) bits hold the section order wire to be inserted in the data stream. the e1v[7:0] value is inserted in the e1 byte of sts-1/stm-0 #1 if the insertion is enabled via the e1regen bit in the trmp register insertion register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 160 register 0085h: trmp transmit d1d3 and d4d12 bit type function default bit 15 r/w d1d3v[7] 0 bit 14 r/w d1d3v[6] 0 bit 13 r/w d1d3v[5] 0 bit 12 r/w d1d3v[4] 0 bit 11 r/w d1d3v[3] 0 bit 10 r/w d1d3v[2] 0 bit 9 r/w d1d3v[1] 0 bit 8 r/w d1d3v[0] 0 bit 7 r/w d4d12v[7] 0 bit 6 r/w d4d12v[6] 0 bit 5 r/w d4d12v[5] 0 bit 4 r/w d4d12v[4] 0 bit 3 r/w d4d12v[3] 0 bit 2 r/w d4d12v[2] 0 bit 1 r/w d4d12v[1] 0 bit 0 r/w d4d12v[0] 0 d4d12v[7:0]: the d4d12 byte value (d4d12v[7:0]) bits hold the line data communication channel to be inserted in the data stream. the d4d12v[7:0] value is inserted in the d4 to d12 bytes of sts-1/stm-0 #1 if the insertion is enabled via the d4d12regen bit in the trmp register insertion register. d1d3v[7:0]: the d1d3 byte value (d1d3v[7:0]) bits hold the section data communication channel to be inserted in the data stream. the d1d3v[7:0] value is inserted in the d1 to d3 bytes of sts- 1/stm-0 #1 if the insertion is enabled via the d1d3regen bit in the trmp register insertion register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 161 register 0086h: trmp transmit k1 and k2 bit type function default bit 15 r/w k1v[7] 0 bit 14 r/w k1v[6] 0 bit 13 r/w k1v[5] 0 bit 12 r/w k1v[4] 0 bit 11 r/w k1v[3] 0 bit 10 r/w k1v[2] 0 bit 9 r/w k1v[1] 0 bit 8 r/w k1v[0] 0 bit 7 r/w k2v[7] 0 bit 6 r/w k2v[6] 0 bit 5 r/w k2v[5] 0 bit 4 r/w k2v[4] 0 bit 3 r/w k2v[3] 0 bit 2 r/w k2v[2] 0 bit 1 r/w k2v[1] 0 bit 0 r/w k2v[0] 0 k1v[7:0], k2v[7:0]: the k1, k2 bytes value (k1v[7:0], k2v[7:0]) bits hold the aps bytes to be inserted in the data stream. the k1v[7:0], k2v[7:0] values are inserted in the k1, k2 bytes of sts-1/stm-0 #1 if the insertion is enabled via the k1k2regen bit in the trmp register insertion register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 162 register 0087h: trmp transmit s1 and z1 bit type function default bit 15 r/w s1v[7] 0 bit 14 r/w s1v[6] 0 bit 13 r/w s1v[5] 0 bit 12 r/w s1v[4] 0 bit 11 r/w s1v[3] 0 bit 10 r/w s1v[2] 0 bit 9 r/w s1v[1] 0 bit 8 r/w s1v[0] 0 bit 7 r/w z1v[7] 0 bit 6 r/w z1v[6] 0 bit 5 r/w z1v[5] 0 bit 4 r/w z1v[4] 0 bit 3 r/w z1v[3] 0 bit 2 r/w z1v[2] 0 bit 1 r/w z1v[1] 0 bit 0 r/w z1v[0] 0 z1v[7:0]: the z1 byte value (z1v[7:0]) bits hold the z1 growth byte to be inserted in the data stream. the z1v[7:0] value is inserted in the z1 byte if the insertion is enabled via the z1regen bit in the trmp register insertion register. s1v[7:0]: the s1 byte value (s1v[7:0]) bits hold the synchronization status message to be inserted in the data stream. the s1v[7:0] value is inserted in the s1 byte of sts-1/stm-0 #1 if the insertion is enabled via the s1regen bit in the trmp register insertion register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 163 register 0088h: trmp transmit z2 and e2 bit type function default bit 15 r/w z2v[7] 0 bit 14 r/w z2v[6] 0 bit 13 r/w z2v[5] 0 bit 12 r/w z2v[4] 0 bit 11 r/w z2v[3] 0 bit 10 r/w z2v[2] 0 bit 9 r/w z2v[1] 0 bit 8 r/w z2v[0] 0 bit 7 r/w e2v[7] 0 bit 6 r/w e2v[6] 0 bit 5 r/w e2v[5] 0 bit 4 r/w e2v[4] 0 bit 3 r/w e2v[3] 0 bit 2 r/w e2v[2] 0 bit 1 r/w e2v[1] 0 bit 0 r/w e2v[0] 0 e2v[7:0]: the e2 byte value (e2[7:0]) bits hold the line order wire to be inserted in the data stream. the e2v[7:0] value is inserted in the e2 byte of sts-1/stm-0 #1 if the insertion is enabled via the e2regen bit in the trmp register insertion register. z2v[7:0]: the z2 byte value (z2v[7:0]) bits hold the z2 growth byte to be inserted in the data stream. the z2v[7:0] value is inserted in the z2 byte if the insertion is enabled via the z2regen bit in the trmp register insertion register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 164 register 0089h: trmp transmit h1 and h2 mask bit type function default bit 15 r/w h1mask[7] 0 bit 14 r/w h1mask[6] 0 bit 13 r/w h1mask[5] 0 bit 12 r/w h1mask[4] 0 bit 11 r/w h1mask[3] 0 bit 10 r/w h1mask[2] 0 bit 9 r/w h1mask[1] 0 bit 8 r/w h1mask[0] 0 bit 7 r/w h2mask[7] 0 bit 6 r/w h2mask[6] 0 bit 5 r/w h2mask[5] 0 bit 4 r/w h2mask[4] 0 bit 3 r/w h2mask[3] 0 bit 2 r/w h2mask[2] 0 bit 1 r/w h2mask[1] 0 bit 0 r/w h2mask[0] 0 h2mask[7:0]: the h2 mask (h2mask[7:0]) bits hold the h2 path payload pointer errors to be inserted in the data stream. the h2mask[7:0] is xored with the path payload pointer already in the data stream. h1mask[7:0]: the h1 mask (h1mask[7:0]) bits hold the h1 path payload pointer errors to be inserted in the data stream. the h1mask[7:0] is xored with the path payload pointer already in the data stream.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 165 register 008a: trmp transmit b1 and b2 mask bit type function default bit 15 r/w b1mask[7] 0 bit 14 r/w b1mask[6] 0 bit 13 r/w b1mask[5] 0 bit 12 r/w b1mask[4] 0 bit 11 r/w b1mask[3] 0 bit 10 r/w b1mask[2] 0 bit 9 r/w b1mask[1] 0 bit 8 r/w b1mask[0] 0 bit 7 r/w b2mask[7] 0 bit 6 r/w b2mask[6] 0 bit 5 r/w b2mask[5] 0 bit 4 r/w b2mask[4] 0 bit 3 r/w b2mask[3] 0 bit 2 r/w b2mask[2] 0 bit 1 r/w b2mask[1] 0 bit 0 r/w b2mask[0] 0 b2mask[7:0]: the b2 mask (b2mask[7:0]) bits hold the b2 bip-8 errors to be inserted in the data stream. the b2mask[7:0] is xored with the calculated b2 before insertion in the b2 byte. b1mask[7:0]: the b1 mask (b1mask[7:0]) bits hold the b1 bip-8 errors to be inserted in the data stream. the b1mask[7:0] is xored with the calculated b1 before insertion in the b1 byte.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 166 register 00a0h: trmp aux2 configuration register 00c0h: trmp aux3 configuration register 00e0h: trmp aux4 configuration bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r/w reserved 0 bit 10 r/w reserved 1 bit 9 r/w reserved 1 bit 8 r/w reserved 1 bit 7 r/w reserved 1 bit 6 r/w reserved 0 bit 5 r/w reserved 1 bit 4 r/w reserved tslden 1 bit 3 r/w reserved 1 bit 2 r/w j0z0incen 0 bit 1 r/w z0def 0 bit 0 r/w a1a2en 1 all reserved bits in this register should be set to logic 0 for normal operation. a1a2en: for normal operation, the a1a2en should be set to the same value as the a1a2en bit in the trmp configuration register. z0def: for normal operation, the z0def should be set to the same value as the z0def bit in the trmp configuration register. j0z0incen: for normal operation, the j0z0incen should be set to the same value as the j0z0incen bit in the trmp configuration register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 167 register 00a2h: trmp aux2 error insertion register 00c2h: trmp aux3 error insertion register 00e2h: trmp aux4 error insertion bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 r/w losins 0 bit 5 r/w laisins 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 1 bit 1 r/w reserved 1 bit 0 r/w reserved 1 all reserved bits in this register should be set to logic 0 for normal operation. laisins: for normal operation, the laisins should be set to the same value as the laisins bit in the trmp error insertion register. losins: for normal operation, the losins should be set to the same value as the losins bit in the trmp error insertion register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 168 register 0110h: sber configuration bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 unused bit 5 r/w sfberten 0 bit 4 r/w sfsmode 0 bit 3 r/w sfcmode 0 bit 2 r/w sdberten 0 bit 1 r/w sdsmode 0 bit 0 r/w sdcmode 0 sdcmode: the sdcmode alarm bit selects the signal degrade berm window size to use for clearing alarms. when sdcmode is a logic 0 the sd berm will clear an alarm using the same window size used for declaration. when sdcmode is a logic 1 the sd berm will clear an alarm using a window size that is 8 times longer than alarm declaration window size. the declaration window size is defined by the sber sd berm accumulation period register. sdsmode: the sdsmode bit selects the signal degrade berm saturation mode. when sdsmode is a logic 0 the sd berm will saturate the bip count on a per frame basis using the sber sd saturation threshold register value. when sdsmode is a logic 1 the sd berm will saturate the bip count on a per window subtotals accumulation period basis using the sber sd saturation threshold register value. sdberten: the sdberten bit enables automatic monitoring of line bit error rate threshold events by the signal degrade berm. when sdberten is a logic one, the sd berm continuously monitors line bip errors over a period defined in the berm configuration registers. when sdberten is a logic zero, the sd berm bip accumulation logic is disabled, and the berm logic is reset to restart in the declaration monitoring state.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 169 all sd berm configuration registers should be set up before the monitoring is enabled. sfcmode: the sfcmode alarm bit selects the signal failure berm window size to use for clearing alarms. when sfcmode is a logic 0 the sf berm will clear an alarm using the same window size used for declaration. when sfcmode is a logic 1 the sf berm will clear an alarm using a window size that is 8 times longer than alarm declaration window size. the declaration window size is defined by the sber sf berm accumulation period register. sfsmode: the sfsmode bit selects the signal failure berm saturation mode. when sfsmode is a logic 0 the sf berm will saturate the bip count on a per frame basis using the sber sf saturation threshold register value. when sfsmode is a logic 1 the sf berm will saturate the bip count on a per window subtotals accumulation period basis using the sber sd saturation threshold register value. sfberten: the sfberten bit enables automatic monitoring of line bit error rate threshold events by the signal failure berm. when sfberten is a logic one, the sf berm continuously monitors line bip errors over a period defined in the berm configuration registers. when sfberten is a logic zero, the sf berm bip accumulation logic is disabled, and the berm logic is reset to restart in the declaration monitoring state. all sf berm configuration registers should be set up before the monitoring is enabled.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 170 register 0111h: sber status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 unused bit 5 unused bit 4 unused bit 3 unused bit 2 unused bit 1 r sfberv x bit 0 r sdberv x sdberv: the sdberv bit indicates the signal failure berm alarm state. the alarm is declared (sdberv is a logic one) when the declaring threshold has been exceeded. the alarm is removed (sdberv is a logic zero) when the clearing threshold has been reached. sfberv: the sfberv bit indicates the signal failure berm alarm state. the alarm is declared (sfberv is a logic one) when the declaring threshold has been exceeded. the alarm is removed (sfberv is a logic zero) when the clearing threshold has been reached.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 171 register 0112h: sber interrupt enable bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 unused bit 5 unused bit 4 unused bit 3 unused bit 2 unused bit 1 r/w sfbere 0 bit 0 r/w sdbere 0 sdbere: the sdbere bit is the interrupt enable for the sdber alarm. when sdbere set to logic 1, the pending interrupt in the sber interrupt status register, sdberi, will assert the interrupt (intb) output. when sdbere is set to logic 0, the pending interrupt will not assert the interrupt (intb) output. sfbere: the sfbere bit is the interrupt enable for the sfber alarm. when sfbere set to logic 1, the pending interrupt in the sber interrupt status register, sfberi, will assert the interrupt (intb) output. when sfbere is set to logic 0, the pending interrupt will not assert the interrupt (intb) output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 172 register 0113h: sber interrupt status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 unused bit 5 unused bit 4 unused bit 3 unused bit 2 unused bit 1 r sfberi x bit 0 r sdberi x sdberi: the sdberi bit is an event indicator set to logic 1 to indicate any changes in the status of sdberv. this interrupt status bit is independent of the sdbere interrupt enable bits. the sdberi bit is cleared to logic 0 when the sber interrupt status register is read. sfberi: the sfberi bit is an event indicator set to logic 1 to indicate any changes in the status of sfberv. this interrupt status bit is independent of the sfbere interrupt enable bits. the sfberi bit is cleared to logic 0 when the sber interrupt status register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 173 register 0114h: sber sf berm accumulation period (lsb) bit type function default bit 15 to bit 0 r/w sfsap[15:0] 0000 register 0115h: sber sf berm accumulation period (msb) bit type function default bit 15 to bit 0 r/w sfsap[31:16] 0000 sfsap[31:0]: the sfsap[31:0] bits represent the number of sts-n frames to be used to accumulate a bip error subtotal. the total evaluation window to declare an alarm is broken into 8 subtotals, so this register value represents 1/8 of the total sliding window size. refer to the operations section for the recommended settings..
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 174 register 0116h: sber sf berm saturation threshold (lsb) bit type function default bit 15 to bit 0 r/w sfsath[15:0] 0000 register 0117h: sber sf berm saturation threshold (msb) bit type function default bit 15 to bit 0 r/w sfsath[31:16] 0000 sfsath[31:0]: the sfsth[31:0] bits represent the allowable number of bip errors that can be accumulated during a bip accumulation period before a ber threshold event is asserted. setting this threshold to 0xffffffff disables the saturation functionality. refer to the operations section for the recommended settings..
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 175 register 0118h: sber sf berm declaring threshold (lsb) bit type function default bit 15 to bit 0 r/w sfdecth[15:0] 0000 register 0119h: sber sf berm declaring threshold (msb) bit type function default bit 15 to bit 0 r/w sfdecth[31:16] 0000 sfdecth[31:0]: the sfdecth[31:0] register represent the number of bip errors that must be accumulated during a full evaluation window in order to declare a ber alarm. refer to the operations section for the recommended settings..
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 176 register 011ah: sber sf berm clearing threshold (lsb) bit type function default bit 15 to bit 0 r/w sfclrth[15:0] 0000 register 011bh: sber sf berm clearing threshold (msb) bit type function default bit 15 to bit 0 r/w sfclrth[31:16] 0000 sfclrth[31:0]: the sfclrth[31:0] register represent the number of bip errors that can be accumulated but not exceeded during a full evaluation window in order to clear a ber alarm. refer to the operations section for the recommended settings..
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 177 register 011ch: sber sd berm accumulation period (lsb) bit type function default bit 15 to bit 0 r/w sdsap[15:0] 0000 register 011dh: sber sd berm accumulation period (msb) bit type function default bit 15 to bit 0 r/w sdsap[31:16] 0000 sdsap[31:0]: the sdsap[31:0] bits represent the number of sts-n frames to be used to accumulate a bip error subtotal. the total evaluation window to declare an alarm is broken into 8 subtotals, so this register value represents 1/8 of the total sliding window size. refer to the operations section for the recommended settings..
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 178 register 011eh: sber sd berm saturation threshold (lsb) bit type function default bit 15 to bit 0 r/w sdsth[15:0] 0000 register 011fh: sber sd berm saturation threshold (msb) bit type function default bit 15 to bit 0 r/w sdsth[31:16] 0000 sdsth[31:0]: the sdsth[31:0] bits represent the allowable number of bip errors that can be accumulated during a bip accumulation period before a ber threshold event is asserted. setting this threshold to 0xffffffff disables the saturation functionality. refer to the operations section for the recommended settings..
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 179 register 0120h: sber sd berm declaration threshold (lsb) bit type function default bit 15 to bit 0 r/w sddecth[15:0] 0000 register 0121h: sber sd berm declaration threshold (msb) bit type function default bit 15 to bit 0 r/w sddecth[31:16] 0000 sddecth[31:0]: the sddecth[31:0] register represent the number of bip errors that must be accumulated during a full evaluation window in order to declare a ber alarm. refer to the operations section for the recommended settings..
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 180 register 0122h: sber sd berm clearing threshold (lsb) bit type function default bit 15 to bit 0 r/w sdclrth[15:0] 0000 register 0123h: sber sd berm clearing threshold (msb) bit type function default bit 15 to bit 0 r/w sdclrth[31:16] 0000 sdclrth[31:0]: the sdclrth[31:0] register represent the number of bip errors that can be accumulated but not exceeded during a full evaluation window in order to clear a ber alarm. refer to the operations section for the recommended settings.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 181 register 0130h: rttp section indirect address bit type function default bit 15 r busy x bit 14 r/w rwb 0 bit 13 r/w iaddr[7] 0 bit 12 r/w iaddr[6] 0 bit 11 r/w iaddr[5] 0 bit 10 r/w iaddr[4] 0 bit 9 r/w iaddr[3] 0 bit 8 r/w iaddr[2] 0 bit 7 r/w iaddr[1] 0 bit 6 r/w iaddr[0] 0 bit 5 unused bit 4 unused bit 3 r/w section[3] 0 bit 2 r/w section[2] 0 bit 1 r/w section[1] 0 bit 0 r/w section[0] 0 section[3:0]: the sts-1/stm-0 section (section[3:0]) bits select which sts-1/stm-0 section is accessed by the current indirect transfer. this register should only be set to 0001 since only the sts-1/stm-0 #1 section byte is valid.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 182 iaddr[7:0]: the indirect address location (iaddr[7:0]) bits select which indirect address location is accessed by the current indirect transfer. indirect address iaddr[7:0] indirect data 0000 0000 configuration 0000 0001 to 0011 1111 invalid address 0100 0000 first byte of the 1/16/64 byte captured trace 0100 0001 to 0111 1111 other bytes of the 16/64 byte captured trace 1000 0000 first byte of the 1/16/64 byte accepted trace 1000 0001 to 1011 1111 other bytes of the 16/64 byte accepted trace 1100 0000 first byte of the 16/64 byte expected trace 1100 0001 to 1111 1111 other bytes of the 16/64 byte expected trace rw b: the active high read and active low write (rwb) bit selects if the current access to the internal ram is an indirect read or an indirect write. writing to the indirect address register initiates an access to the internal ram. when rwb is set to logic 1, an indirect read access to the ram is initiated. the data from the addressed location in the internal ram will be transferred to the indirect data register. when rwb is set to logic 0, an indirect write access to the ram is initiated. the data from the indirect data register will be transferred to the addressed location in the internal ram. busy: the active high ram busy (busy) bit reports if a previously initiated indirect access to the internal ram has been completed. busy is set to logic 1 upon writing to the indirect address register. busy is set to logic 0, upon completion of the ram access. this register should be polled to determine when new data is available in the indirect data register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 183 register 0131h: rttp section indirect data bit type function default bit 15 r/w data[15] 0 bit 14 r/w data[14] 0 bit 13 r/w data[13] 0 bit 12 r/w data[12] 0 bit 11 r/w data[11] 0 bit 10 r/w data[10] 0 bit 9 r/w data[9] 0 bit 8 r/w data[8] 0 bit 7 r/w data[7] 0 bit 6 r/w data[6] 0 bit 5 r/w data[5] 0 bit 4 r/w data[4] 0 bit 3 r/w data[3] 0 bit 2 r/w data[2] 0 bit 1 r/w data[1] 0 bit 0 r/w data[0] 0 data[15:0]: the indirect access data (data[15:0]) bits hold the data transfer to or from the internal ram during indirect access. when rwb is set to logic 1 (indirect read), the data from the addressed location in the internal ram will be transfer to data[15:0]. busy should be polled to determine when the new data is available in data[15:0]. when rwb is set to logic 0 (indirect write), the data from data[15:0] will be transfer to the addressed location in the internal ram. the indirect data register must contain valid data before the indirect write is initiated by writing to the indirect address register. data[15:0] has a different meaning depending on which address of the internal ram is being accessed.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 184 register 0132h: rttp section trace unstable status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r reserve x bit 10 r reserve x bit 9 r reserve x bit 8 r reserve x bit 7 r reserve x bit 6 r reserve x bit 5 r reserve x bit 4 r reserve x bit 3 r reserve x bit 2 r reserve x bit 1 r reserve x bit 0 r tiuv[1] x tiuv[1]: the trace identifier unstable status (tiuv[1]) bit indicates the current status of the tiu defect. algorithm 1: tiuv is set to logic 0. algorithm 2: tiuv is set to logic 1 when one or more erroneous bytes are detected between the current message and the previous message in a total of 8 tail trace messages without any persistent message in between. tiuv is set to logic 0 when a persistent message is found. a persistent message is found when the same message is receive for 3 or 5 consecutive multi-frames. algorithm 3: tiuv is set to logic 1 when one or more erroneous bytes are detected in three consecutive sixteen byte windows. the first window starts on the first erroneous tail trace byte. byte_tiuv is set to logic 0 when the same tail trace byte is received for 48 consecutive frames.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 185 register 0133h: rttp section trace unstable interrupt enable bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r/w reserved 0 bit 10 r/w reserved 0 bit 9 r/w reserved 0 bit 8 r/w reserved 0 bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w tiue[1] 0 tiue[1]: the trace identifier unstable interrupt enable (tiue[1]) bit controls the activation of the interrupt (intb) output. when the bit is set to logic 1, the corresponding pending interrupt will assert the interrupt (intb) output. when the bit is set to logic 0, the corresponding pending interrupt will not assert the interrupt (intb) output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 186 register 0134h: rttp section trace unstable interrupt status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r reserve x bit 10 r reserve x bit 9 r reserve x bit 8 r reserve x bit 7 r reserve x bit 6 r reserve x bit 5 r reserve x bit 4 r reserve x bit 3 r reserve x bit 2 r reserve x bit 1 r reserve x bit 0 r tiui[1] x tiui[1]: the trace identifier unstable interrupt status (tiui[1]) bit is an event indicator. tiui[1] is set to logic 1 to indicate any changes in the status of tiuv[1] (stable to unstable, unstable to stable). this interrupt status bit is independent of the interrupt enable bit. tiui[1] is cleared to logic 0 when this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 187 register 0135h: rttp section trace mismatch status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r reserve x bit 10 r reserved x bit 9 r reserved x bit 8 r reserved x bit 7 r reserved x bit 6 r reserved x bit 5 r reserved x bit 4 r reserved x bit 3 r reserved x bit 2 r reserved x bit 1 r reserved x bit 0 r timv[1] x timv[1]: the trace identifier mismatch status (timv[1]) bit indicates the current status of the tim defect. algorithm 1: timv is set to logic 1 when none of the last 20 messages matches the expected message. timv is set to logic 0 when 16 of the last 20 messages match the expected message. algorithm 2: timv is set to logic 1 when the accepted message does not match the expected message. timv is set to logic 0 when the accepted message matches the expected message. algorithm 3: timv is set to logic 0.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 188 register 0136h: rttp section trace mismatch interrupt enable bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r/w reserve 0 bit 10 r/w reserve 0 bit 9 r/w reserve 0 bit 8 r/w reserve 0 bit 7 r/w reserve 0 bit 6 r/w reserve 0 bit 5 r/w reserved 0 bit 4 r/w reserve 0 bit 3 r/w reserve 0 bit 2 r/w reserve 0 bit 1 r/w reserve 0 bit 0 r/w time[1] 0 time[1]: the trace identifier mismatch interrupt enable (time[1]) bit controls the activation of the interrupt (intb) output. when set to logic 1, the corresponding pending interrupt will assert the interrupt (intb) output. when set to logic 0, the corresponding pending interrupt will not assert the interrupt (intb) output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 189 register 0137h: rttp section trace mismatch interrupt status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r reserve x bit 10 r reserve x bit 9 r reserve x bit 8 r reserve x bit 7 r reserve x bit 6 r reserve x bit 5 r reserve x bit 4 r reserve x bit 3 r reserve x bit 2 r reserve x bit 1 r reserve x bit 0 r timi[1] x timi[1]: the trace identifier mismatch interrupt status (timi[1]) bit is an event indicator. timi[1] is set to logic 1 to indicate any changes in the status of timv[1] (match to mismatch, mismatch to match). this interrupt status bit is independent of the interrupt enable bit. timi[1] is cleared to logic 0 when this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 190 indirect register 00h: rttp section trace configuration bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 unused bit 5 r/w zeroen 0 bit 4 r/w per5 0 bit 3 r/w nosync 0 bit 2 r/w length16 0 bit 1 r/w algo[1] 0 bit 0 r/w algo[0] 0 algo[1:0]: the tail trace algorithm select (algo[1:0]) bits select the algorithm used to process the tail trace message. algo[1:0] tail trace algorithm 00 algorithm disable 01 algorithm 1 10 algorithm 2 11 algorithm 3 when algo[1:0] is set to logic 00b, the tail trace algorithms are disable. the corresponding tiuv, timv register bits and the corresponding tiu, tim output signal time slots are set to logic 0. length16: the message length (length16) bit selects the length of the tail trace message use by algorithm 1 and algorithm 2. when length16 is set to logic 1, the length of the tail trace message is 16 byte. when length16 is set to logic 0, the length of the tail trace message is 64 byte.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 191 nosync: the synchronization disable (nosync) bit disables the synchronization of the tail trace message in algorithm 1 and algorithm 2. when nosync is set to logic 1, no synchronization is done on the tail trace message. the bytes of the tail trace message are written in the captured page as in a circular buffer. when nosync is set to logic 0, synchronization is done on the tail trace message. when length16 is set to logic 1, the tail trace message is synchronize on the msb of the tail trace message. the byte with its msb set high is placed in the first byte location of the captured page. when length16 is set to logic 0, the tail trace message is synchronize on the cr/lf (cr = 0dh, lf = 0ah) characters of the tail trace message. the byte following the cr/lf bytes is placed in the first byte location of the captured page. per5: the message persistency (per5) bit selects the number of multi-frames a tail trace message must be received in order to be declared persistent in algorithm 2. when per5 is set to logic 1, the same tail trace message must be receive for 5 consecutive multi-frames to be declared persistent. when per5 is set to logic 0, the same tail trace message must be received for 3 consecutive multi frame to be declared persistent. zeroen: the all zero message enable (zeroen) bit selects if the all zero message are validated or not against the expected message in algorithm 1 and algorithm 2. when zeroen is set to logic 1, an all zero captured message in algorithm 1 and an all zero accepted message in algorithm 2 are validated against the expected message. a match is declared when both the captured/accepted message and the expected message are all zero. when zeroen is set to logic 0, an all zero captured message in algorithm 1 and an all zero accepted message in algorithm 2 are not validated against the expected message but are considered match. a match is declared when the captured/accepted message is all zero regardless of the expected message.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 192 indirect register 40h to 7fh: rttp section captured trace bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 r/w ctrace[7] x bit 6 r/w ctrace[6] x bit 5 r/w ctrace[5] x bit 4 r/w ctrace[4] x bit 3 r/w ctrace[3] x bit 2 r/w ctrace[2] x bit 1 r/w ctrace[1] x bit 0 r/w ctrace[0] x the rttp section captured trace indirect register is provided at rttp r/w indirect address 40h to 7fh. ctrace[7:0]: the captured tail trace message (ctrace[7:0]) bits contain the currently received tail trace message. when algorithm 1 or 2 is selected and length16 is set to logic 1, the captured message is stored between address 40h and 4fh. when algorithm 1 or 2 is selected and length16 is set to logic 0, the captured message is stored between address 40h and 7fh. when nosync is set to logic 1, the captured message is not synchronize. when nosync is set to logic 0, the captured message is synchronized and the first byte of the message is stored at address 40h. when algorithm 3 is selected, the captured byte is stored at address 40h.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 193 indirect register 80h to bfh: rttp section accepted trace bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 r/w atrace[7] x bit 6 r/w atrace[6] x bit 5 r/w atrace[5] x bit 4 r/w atrace[4] x bit 3 r/w atrace[3] x bit 2 r/w atrace[2] x bit 1 r/w atrace[1] x bit 0 r/w atrace[0] x the rttp section accepted trace indirect register is provided at rttp r/w indirect address 80h to bfh. atrace[7:0]: the accepted tail trace message (atrace[7:0]) bits contain the persistent tail trace message. when algorithm 2 is selected and per5 is set to logic 1, the accepted message is the same tail trace message received for 5 consecutive multi-frames. when algorithm 2 is selected and per5 is set to logic 0, the accepted message is the same tail trace message received for 3 consecutive multi-frames. when algorithm 2 is selected and length16 is set to logic 1, the accepted message is stored between address 80h and 8fh. when algorithm 2 is selected and length16 is set to logic 0, the accepted message is stored between address 80h and bfh. when algorithm 3 is selected, the accepted byte is the same tail trace byte received for 48 frames. when algorithm 3 is selected, the accepted byte is stored at address 80h.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 194 indirect register c0h to ffh: rttp section expected trace bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 r/w etrace[7] x bit 6 r/w etrace[6] x bit 5 r/w etrace[5] x bit 4 r/w etrace[4] x bit 3 r/w etrace[3] x bit 2 r/w etrace[2] x bit 1 r/w etrace[1] x bit 0 r/w etrace[0] x the rttp section expected trace indirect register is provided at rttp r/w indirect address c0h to ffh. etrace[7:0]: the expected tail trace message (etrace[7:0]) bits contain a static message written by an external microprocessor. in algorithm 1 the expected message is used to validated the captured message. in algorithm 2 the expected message is used to validate the accepted message. when length16 is set to logic 1, the expected message must be written between address c0h and cfh. when length16 is set to logic 0, the accepted message must be written between address c0h and ffh.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 195 register 0138h: tttp section indirect address bit type function default bit 15 r busy x bit 14 r/w rwb 0 bit 13 unused bit 12 r/w iaddr[6] 0 bit 11 r/w iaddr[5] 0 bit 10 r/w iaddr[4] 0 bit 9 r/w iaddr[3] 0 bit 8 r/w iaddr[2] 0 bit 7 r/w iaddr[1] 0 bit 6 r/w iaddr[0] 0 bit 5 unused bit 4 unused bit 3 r/w section[3] 0 bit 2 r/w section[2] 0 bit 1 r/w section[1] 0 bit 0 r/w section[0] 0 section[3:0]: the sts-1/stm-0 section (section[3:0]) bits select which sts-1/stm-0 is accessed by the current indirect transfer. section[3:0] should be set to 0001.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 196 iaddr[6:0]: the indirect address location (iaddr[6:0]) bits select which indirect address location is accessed by the current indirect transfer. indirect address iaddr[6:0] indirect data 000 0000 configuration 000 0001 to 011 1111 invalid address 100 0000 first byte of the 1/16/64 byte trace 100 0001 to 111 1111 other bytes of the 16/64 byte trace rw b: the active high read and active low write (rwb) bit selects if the current access to the internal ram is an indirect read or an indirect write. writing to the indirect address register initiates an access to the internal ram. when rwb is set to logic 1, an indirect read access to the ram is initiated. the data from the addressed location in the internal ram will be transferred to the indirect data register. when rwb is set to logic 0, an indirect write access to the ram is initiated. the data from the indirect data register will be transferred to the addressed location in the internal ram. busy: the active high ram busy (busy) bit reports if a previously initiated indirect access to the internal ram has been completed. busy is set to logic 1 upon writing to the indirect address register. busy is set to logic 0, upon completion of the ram access. this register should be polled to determine when new data is available in the indirect data register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 197 register 0139h: tttp section indirect data bit type function default bit 15 r/w data[15] 0 bit 14 r/w data[14] 0 bit 13 r/w data[13] 0 bit 12 r/w data[12] 0 bit 11 r/w data[11] 0 bit 10 r/w data[10] 0 bit 9 r/w data[9] 0 bit 8 r/w data[8] 0 bit 7 r/w data[7] 0 bit 6 r/w data[6] 0 bit 5 r/w data[5] 0 bit 4 r/w data[4] 0 bit 3 r/w data[3] 0 bit 2 r/w data[2] 0 bit 1 r/w data[1] 0 bit 0 r/w data[0] 0 data[15:0]: the indirect access data (data[15:0]) bits hold the data transfer to or from the internal ram during indirect access. when rwb is set to logic 1 (indirect read), the data from the addressed location in the internal ram will be transfer to data[15:0]. busy should be polled to determine when the new data is available in data[15:0]. when rwb is set to logic 0 (indirect write), the data from data[15:0] will be transferred to the addressed location in the internal ram. the indirect data register must contain valid data before the indirect write is initiated by writing to the indirect address register. data[15:0] has a different meaning depending on which address of the internal ram is being accessed.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 198 indirect register 0138h: tttp section trace configuration bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 unused bit 5 unused bit 4 unused bit 3 unused bit 2 r/w zeroen 0 bit 1 r/w byteen 0 bit 0 r/w length16 0 length16: the message length (length16) bit selects the length of the tail trace message to be transmitted. when length16 is set to logic 1, the length of the tail trace message is 16 byte. when length16 is set to logic 0, the length of the tail trace message is 64 byte. byteen: the single byte message enable (byteen) bit enables the single byte tail trace message. when byteen is set to logic 1, the length of the tail trace message is 1 byte. when byteen is set to logic 0, the length of the tail trace message is determined by length16. byteen has precedence over length16. zeroen: the all zero message enable (zeroen) bit enables the transmission of an all zero tail trace message. when zeroen is set to logic 1, an all zero message is transmitted. when zeroen is set to logic 0, the ram message is transmitted. the enabling and disabling of the all zero tail trace message is not done on message boundary since the receiver is required to perform filtering on the message.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 199 indirect register 40h to 7fh: tttp section trace bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 r/w trace[7] x bit 6 r/w trace[6] x bit 5 r/w trace[5] x bit 4 r/w trace[4] x bit 3 r/w trace[3] x bit 2 r/w trace[2] x bit 1 r/w trace[1] x bit 0 r/w trace[0] x trace[7:0]: the tail trace message (trace[7:0]) bits contain the tail trace message to be transmitted. when byteen is set to logic 1, the message is stored at indirect register address 40h. when byteen is set to logic 0 and length16 is set to logic 1, the message is stored between indirect register address 40h and 4fh. when byteen is set to logic 0 and length16 is set to logic 0, the message is stored between indirect register address 40h and 7fh.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 200 register 0200h: rhpp sts-1/stm-0 #1 through #12 indirect address register 0280h: rhpp sts-1/stm-0 #13 through #24 indirect address register 0300h: rhpp sts-1/stm-0 #25 through #36 indirect address register 0380h: rhpp sts-1/stm-0 #37 through #48 indirect address bit type function default bit 15 r busy x bit 14 r/w rwb 0 bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 r/w iaddr[2] 0 bit 7 r/w iaddr[1] 0 bit 6 r/w iaddr[0] 0 bit 5 unused bit 4 unused bit 3 r/w path[3] 0 bit 2 r/w path[2] 0 bit 1 r/w path[1] 0 bit 0 r/w path[0] 0 path[3:0]: the sts-1/stm-0 path (path[3:0]) bits select which sts-1/stm-0 path is accessed by the current indirect transfer. path[3:0] sts-1/stm-0 path # 0000 invalid path 0001 path #(1, 13, 25 or 37) 0010 path #(2, 14, 26 or 38) 0011 path #(3, 15, 27 or 39) 0100 path #(4, 16, 28 or 40) 0101 path #(5, 17, 29 or 41) 0110 path #(6, 18, 30 or 42) 0111 path #(7, 19, 31 or 43) 1000 path #(8, 20, 32 or 44) 1001 path #(9, 21, 33 or 45) 1010 path #(10, 22, 34 or 46)
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 201 1011 path #(11, 23, 35 or47) 1100 path #(12, 24, 36 or 48) 1101- 1111 invalid path iaddr[2:0]: the address location (iaddr[2:0]) bits select which address location is accessed by the current indirect transfer. indirect address iaddr[2:0] indirect data 000 pointer interpreter configuration 001 error monitor configuration 010 pointer value and erdi 011 captured and accepted psl 100 expected psl and pdi 101 gpo and status 101 to 111 unused rw b: the active high read and active low write (rwb) bit selects if the current access to a internal register is an indirect read or an indirect write. writing to the indirect address register initiates an access to a register. when rwb is set to logic 1, an indirect read access to a register is initiated. the data from the addressed location as indicated using the iaddr field will be transferred to the indirect data register. when rwb is set to logic 0, an indirect write access to a register is initiated. the data from the indirect data register will be transferred to the addressed register. busy: the active high busy (busy) bit reports if a previously initiated indirect access to an internal register has been completed. busy is set to logic 1 upon writing to the indirect address register. busy is set to logic 0, upon completion of the access. this register should be polled to determine when new data is available in the indirect data register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 202 register 0201h: rhpp sts-1/stm-0 #1 through #12 indirect data register 0281h: rhpp sts-1/stm-0 #13 through #24 indirect data register 0301h: rhpp sts-1/stm-0 #25 through #36 indirect data register 0381h: rhpp sts-1/stm-0 #37 through #48 indirect data bit type function default bit 15 r/w data[15] 0 bit 14 r/w data[14] 0 bit 13 r/w data[13] 0 bit 12 r/w data[12] 0 bit 11 r/w data[11] 0 bit 10 r/w data[10] 0 bit 9 r/w data[9] 0 bit 8 r/w data[8] 0 bit 7 r/w data[7] 0 bit 6 r/w data[6] 0 bit 5 r/w data[5] 0 bit 4 r/w data[4] 0 bit 3 r/w data[3] 0 bit 2 r/w data[2] 0 bit 1 r/w data[1] 0 bit 0 r/w data[0] 0 data[15:0]: the indirect access data (data[15:0]) bits hold the data transfer to or from an indirect register during indirect access. when rwb is set to logic 1 (indirect read), the data from the addressed location in the register will be transferred to data[15:0]. busy should be polled to determine when the new data is available in data[15:0]. when rwb is set to logic 0 (indirect write), the data from data[15:0] will be transferred to the register. the indirect data register must contain valid data before the indirect write is initiated by writing to the indirect address register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 203 register 0208h, 0210h, 0218h, 0220h, 0228h, 0230h, 0238h, 0240h, 0248h, 0250h, 0258h, 0260h register 0288h, 0290h, 0298h, 02a0h, 02a8h, 02b0h, 02b8h, 02c0h, 02c8h, 02d0h, 02d8h, 02e0h register 0308h, 0310h, 0318h, 0320h, 0328h, 0330h, 0338h, 0340h, 0348h, 0350h, 0358h, 0360h register 0388h, 0390h, 0398h, 03a0h, 03a8h, 03b0h, 03b8h, 03c0h, 03c8h, 03d0h, 03d8h, 03e0h: rhpp sts-1/stm-0 #n (where n=1 to 48) pointer interpreter status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 unused bit 5 r paiscv x bit 4 r plopcv x bit 3 r paisv x bit 2 r plopv x bit 1 unused bit 0 unused plopv: the path lost of pointer state (plopv) bit indicates the current status of the pointer interpreter state machine. plopv is set to logic 1 when the state machine is in the lop_state. plopv is set to logic 0 when the state machine is not in the lop_state. this bit is only valid for rhpp sts-1/stm0 #1. paisv: the path alarm indication signal state (paisv) bit indicates the current status of the pointer interpreter state machine. paisv is set to logic 1 when the state machine is in the ais_state. paisv is set to logic 0 when the state machine is not in the ais_state. this bit is only valid for rhpp sts-1/stm0 #1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 204 plopcv: the path lost of pointer concatenation state (plopcv) bit indicates the current status of the concatenation pointer interpreter state machine. plopcv is set to logic 1 when the state machine is in the lopc_state. plopcv is set to logic 0 when the state machine is not in the lopc_state. this bit is only valid for rhpp sts-1/stm0 #2-48. paiscv: the path concatenation alarm indication signal state (paiscv) bit indicates the current status of the concatenation pointer interpreter state machine. paiscv is set to logic 1 when the state machine is in the aisc_state. paiscv is set to logic 0 when the state machine is not in the lopc_state. this bit is only valid for rhpp sts-1/stm0 #2-48.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 205 register 0209h, 0211h, 0219h, 0221h, 0229h, 0231h, 0239h, 0241h, 0249h, 0251h, 0259h, 0261h register 0289h, 0291h, 0299h, 02a1h, 02a9h, 02b1h, 02b9h, 02c1h, 02c9h, 02d1h, 02d9h, 02e1h register 0309h, 0311h, 0319h, 0321h, 0329h, 0331h, 0339h, 0341h, 0349h, 0351h, 0359h, 0361h register 0389h, 0391h, 0399h, 03a1h, 03a9h, 03b1h, 03b9h, 03c1h, 03c9h, 03d1h, 03d9h, 03e1h: rhpp sts-1/stm-0 #n (where n=1 to 48) pointer interpreter interrupt enable bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 unused bit 5 r/w paisce 0 bit 4 r/w plopce 0 bit 3 r/w paise 0 bit 2 r/w plope 0 bit 1 unused bit 0 r/w ptrjee 0 ptrjee: the pointer justification event interrupt enable (ptrjee) bit control the activation of the interrupt (intb) output. when ptrjee is set to logic 1, the njei and pjei pending interrupt will assert the interrupt (intb) output. when ptrjee is set to logic 0, the njei and pjei pending interrupt will not assert the interrupt (intb) output. this bit is only valid for rhpp sts-1/stm0 #1. plope: the path loss of pointer interrupt enable (plope) bit controls the activation of the interrupt (intb) output. when plope is set to logic 1, the plopi pending interrupt will assert the interrupt (intb) output. when plope is set to logic 0, the plopi pending interrupt will not assert the interrupt (intb) output. this bit is only valid for rhpp sts-1/stm0 #1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 206 paise: the path alarm indication signal interrupt enable (paise) bit controls the activation of the interrupt (intb) output. when paise is set to logic 1, the paisi pending interrupt will assert the interrupt (intb) output. when paise is set to logic 0, the paisi pending interrupt will not assert the interrupt (intb) output. this bit is only valid for rhpp sts-1/stm0 #1. plopce: the path loss of pointer concatenation interrupt enable (plopce) bit controls the activation of the interrupt (intb) output. when plopce is set to logic 1, the plopci pending interrupt will assert the interrupt (intb) output. when plopce is set to logic 0, the plopci pending interrupt will not assert the interrupt (intb) output. this bit is only valid for rhpp sts-1/stm0 #2-48. paisce: the path concatenation alarm indication signal interrupt enable (paisce) bit controls the activation of the interrupt (intb) output. when paisce is set to logic 1, the paisci pending interrupt will assert the interrupt (intb) output. when paisce is set to logic 0, the paisci pending interrupt will not assert the interrupt (intb) output. this bit is only valid for rhpp sts-1/stm0 #2-48.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 207 register 020ah, 0212h, 021ah, 0222h, 022ah, 0232h, 023ah, 0242h, 024ah, 0252h, 025ah, 0262h register 028ah, 0292h, 029ah, 02a2h, 02aah, 02b2h, 02bah, 02c2h, 02cah, 02d2h, 02dah, 02e2h register 030ah, 0312h, 031ah, 0322h, 032ah, 0332h, 033ah, 0342h, 034ah, 0352h, 035ah, 0362h register 038ah, 0392h, 039ah, 03a2h, 03aah, 03b2h, 03bah, 03c2h, 03cah, 03d2h, 03dah, 03e2h: rhpp sts-1/stm-0 #n (where n=1 to 48) pointer interpreter interrupt status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 unused bit 5 r paisci x bit 4 r plopci x bit 3 r paisi x bit 2 r plopi x bit 1 r pjei x bit 0 r njei x njei: the negative pointer justification event interrupt status (njei) bit is an event indicator. njei is set to logic 1 to indicate a negative pointer justification event. the interrupt status bit is independent of the interrupt enable bit. njei is cleared to logic 0 when this register is read. this bit is only valid for rhpp sts-1/stm0 #1. pjei: the positive pointer justification event interrupt status (pjei) bit is an event indicator. pjei is set to logic 1 to indicate a positive pointer justification event. the interrupt status bit is independent of the interrupt enable bit. pjei is cleared to logic 0 when this register is read. this bit is only valid for rhpp sts-1/stm0 #1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 208 plopi: the path loss of pointer interrupt status (plopi) bit is an event indicator. plopi is set to logic 1 to indicate any change in the status of plopv (entry to the lop_state or exit from the lop_state). the interrupt status bit is independent of the interrupt enable bit. plopi is cleared to logic 0 when this register is read. this bit is only valid for rhpp sts-1/stm0 #1. paisi: the path alarm indication signal interrupt status (paisi) bit is an event indicator. paisi is set to logic 1 to indicate any change in the status of paisv (entry to the ais_state or exit from the ais_state). the interrupt status bit is independent of the interrupt enable bit. paisi is cleared to logic 0 when this register is read. this bit is only valid for rhpp sts-1/stm0 #1. plopci: the path loss of pointer concatenation interrupt status (plopci) bit is an event indicator. plopci is set to logic 1 to indicate any change in the status of plopcv (entry to the lopc_state or exit from the lopc_state). the interrupt status bit is independent of the interrupt enable bit. plopci is cleared to logic 0 when this register is read. this bit is only valid for rhpp sts-1/stm0 #2-48. paisci: the path concatenation alarm indication signal interrupt status (paisci) bit is an event indicator. paisci is set to logic 1 to indicate any change in the status of paiscv (entry to the aisc_state or exit from the aisc_state). the interrupt status bit is independent of the interrupt enable bit. paisci is cleared to logic 0 when this register is read. this bit is only valid for rhpp sts-1/stm0 #2-48.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 209 register 020b: rhpp sts-1/stm-0 #1 error monitor status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 r perdiv x bit 5 r prdiv x bit 4 r ppdiv x bit 3 r puneqv x bit 2 r pplmv x bit 1 r ppluv x bit 0 unused ppluv: the path payload label unstable status (ppluv) bit indicates the current status of the plu-p defect. algorithm 1: ppluv is set to logic 0. algorithm 2: ppluv is set to logic 1 when a total of 5 received psl differs from the previously received psl without any persistent psl in between. ppluv is set to logic 0 when a persistent psl is found. a persistent psl is found when the same psl is received for 3 or 5 consecutive frames. pplmv: the path payload label mismatch status (pplmv) bit indicates the current status of the plm- p defect. algorithm 1: pplmv is set to logic 1 when the received psl does not match, according to table 1, the expected psl for 3 or 5 consecutive frames (selectable with the psl5 register bit). pplmv is set to logic 0 when the received psl matches, according to table 1, the expected psl for 3 or 5 consecutive frames.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 210 algorithm 2: pplmv is set to logic 1 when the accepted psl does not match, according to table 1, the expected psl. pplmv is set to logic 0 when the accepted psl matches, according to table 1, the expected psl. puneqv: the path unequipped status (puneqv) bit indicates the current status of the uneq-p defect. puneqv is set to logic 1 when the received psl indicates unequipped, according to table 1, for 3 or 5 consecutive frames (selectable with the psl5 register bit). an puneqv is set to logic 0 when the received psl indicates not unequipped, according to table 1, for 3 or 5 consecutive frames. ppdiv: the path payload defect indication status (ppdiv) bit indicates the current status of the ppdi- p defect. algorithm 1: ppdiv is set to logic one when the received psl is a pdi that does not match, according to table 1, the expected pdi for 3 or 5 consecutive frames (selectable with the psl5 register bit). ppdiv is set to logic 0 when the received psl is a pdi that matches, according to table 1, the expected pdi for 3 or 5 consecutive frames. algorithm 2: ppdiv is set to logic 1 when the accepted psl is a pdi that does not match, according to table 1, the expected pdi. ppdi is set to logic 0 when the accepted psl is a pdi that matches, according to table 1, the expected pdi. prdiv: the path remote defect indication status (prdiv) bit indicates the current status of the rdi-p defect. prdiv is set to logic 1 when bit 5 of the g1 byte is set high for five or ten consecutive frames (selectable with the prdi10 register bit). prdiv is set to logic 0 when bit 5 of the g1 byte is set low for five or ten consecutive frames. perdiv: the path enhanced remote defect indication status (perdiv) bit indicates the current status of the erdi-p defect. perdiv is set to logic 1 when the same 010, 100, 101, 110 or 111 pattern is detected in bits 5, 6 and 7 of the g1 byte for five or ten consecutive frames (selectable with the prdi10 register bit). perdiv is set to logic 0 when the same 000, 001 or 011 pattern is detected in bits 5, 6 and 7 of the g1 byte for five or ten consecutive frames.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 211 register 020c: rhpp sts-1/stm-0 #1 error monitor interrupt enable bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 r/w preiee 0 bit 8 r/w pbipee 0 bit 7 r/w coperdie 0 bit 6 r/w perdie 0 bit 5 r/w prdie 0 bit 4 r/w ppdie 0 bit 3 r/w puneqe 0 bit 2 r/w pplme 0 bit 1 r/w pplue 0 bit 0 r/w copsle 0 copsle: the change of path payload signal label interrupt enable (copsle) bit controls the activation of the interrupt (intb) output. when copsle is set to logic 1, the copsli pending interrupt will assert the interrupt (intb) output. when copsle is set to logic 0, the copsli pending interrupt will not assert the interrupt (intb) output. pplue: the path payload label unstable interrupt enable (pplue) bit controls the activation of the interrupt (intb) output. when pplue is set to logic 1, the pplui pending interrupt will assert the interrupt (intb) output. when pplue is set to logic 0, the pplui pending interrupt will not assert the interrupt (intb) output. pplme: the path payload label mismatch interrupt enable (pplme) bit controls the activation of the interrupt (intb) output. when pplme is set to logic 1, the pplmi pending interrupt will assert the interrupt (intb) output. when pplme is set to logic 0, the pplmi pending interrupt will not assert the interrupt (intb) output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 212 puneqe: the path payload unequipped interrupt enable (puneqe) bit controls the activation of the interrupt (intb) output. when puneqe is set to logic 1, the puneqi pending interrupt will assert the interrupt (intb) output. when puneqe is set to logic 0, the puneqi pending interrupt will not assert the interrupt (intb) output. ppdie: the path payload defect indication interrupt enable (ppdie) bit controls the activation of the interrupt (intb) output. when ppdie is set to logic 1, the ppdi pending interrupt will assert the interrupt (intb) output. when ppdie is set to logic 0, the ppdi pending interrupt will not assert the interrupt (intb) output. prdie: the path remote defect indication interrupt enable (prdie) bit controls the activation of the interrupt (intb) output. when prdie is set to logic 1, the prdii pending interrupt will assert the interrupt (intb) output. when prdie is set to logic 0, the prdii pending interrupt will not assert the interrupt (intb) output. perdie: the path enhanced remote defect indication interrupt enable (perdie) bit controls the activation of the interrupt (intb) output. when perdie is set to logic 1, the perdii pending interrupt will assert the interrupt (intb) output. when perdie is set to logic 0, the perdii pending interrupt will not assert the interrupt (intb) output. coperdie: the change of path enhanced remote defect indication interrupt enable (coperdie) bit controls the activation of the interrupt (intb) output. when coperdie is set to logic 1, the coperdii pending interrupt will assert the interrupt (intb) output. when coperdie is set to logic 0, the coperdii pending interrupt will not assert the interrupt (intb) output. pbipee: the path bip-8 error interrupt enable (pbipee) bit controls the activation of the interrupt (intb) output. when pbipee is set to logic 1, the pbipei pending interrupt will assert the interrupt (intb) output. when pbipee is set to logic 0, the pbipei pending interrupt will not assert the interrupt (intb) output. preiee: the path rei error interrupt enable (preiee) bit controls the activation of the interrupt (intb) output. when preiee is set to logic 1, the preiei pending interrupt will assert the interrupt (intb) output. when preiee is set to logic 0, the preiei pending interrupt will not assert the interrupt (intb) output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 213 register 020d: rhpp sts-1/stm-0 #1 error monitor interrupt status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 r preiei x bit 8 r pbipei x bit 7 r coperdii x bit 6 r perdii x bit 5 r prdii x bit 4 r ppdii x bit 3 r puneqi x bit 2 r pplmi x bit 1 r pplui x bit 0 r copsli x copsli: the change of path payload signal label interrupt status (copsli) bit is an event indicator. copsli is set to logic 1 to indicate a new psl-p value. the interrupt status bit is independent of the interrupt enable bit. copsli is cleared to logic 0 when this register is read. algo2 register bit has no effect on copsli. pplui: the path payload label unstable interrupt status (pplui) bit is an event indicator. pplui is set to logic 1 to indicate any change in the status of ppluv (stable to unstable or unstable to stable). the interrupt status bit is independent of the interrupt enable bit. pplui is cleared to logic 0 when this register is read. pplmi: the path payload label mismatch interrupt status (pplmi) bit is an event indicator. pplmi is set to logic 1 to indicate any change in the status of pplmv (match to mismatch or mismatch to match). the interrupt status bit is independent of the interrupt enable bit. pplmi is cleared to logic 0 when this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 214 puneqi: the path payload unequipped interrupt status (puneqi) bit is an event indicator. puneqi is set to logic 1 to indicate any change in the status of puneqv (equipped to unequipped or unequipped to equipped). the interrupt status bit is independent of the interrupt enable bit. puneqi is cleared to logic 0 when this register is read. ppdii: the path payload defect indication interrupt status (ppdii) bit is an event indicator. ppdii is set to logic 1 to indicate any change in the status of ppdiv (no defect to payload defect or payload defect to no defect). the interrupt status bit is independent of the interrupt enable bit. ppdii is cleared to logic 0 when this register is read. prdii: the path remote defect indication interrupt status (prdii) bit is an event indicator. prdii is set to logic 1 to indicate any change in the status of prdiv (no defect to rdi defect or rdi defect to no defect). the interrupt status bit is independent of the interrupt enable bit. prdii is cleared to logic 0 when this register is read. perdii: the path enhanced remote defect indication interrupt status (perdii) bit is an event indicator. perdii is set to logic 1 to indicate any change in the status of perdiv (no defect to erdi defect or erdi defect to no defect). the interrupt status bit is independent of the interrupt enable bit. perdii is cleared to logic 0 when this register is read. coperdii: the change of path enhanced remote defect indication interrupt status (coperdii) bit is an event indicator. coperdii is set to logic 1 to indicate a new erdi-p value. the interrupt status bit is independent of the interrupt enable bit. coperdii is cleared to logic 0 when this register is read. pbipei: the path bip-8 error interrupt status (pbipei) bit is an event indicator. pbipei is set to logic 1 to indicate a path bip-8 error. the interrupt status bit is independent of the interrupt enable bit. pbipei is cleared to logic 0 when this register is read. preiei: the path rei error interrupt status (preiei) bit is an event indicator. preiei is set to logic 1 to indicate a path rei error. the interrupt status bit is independent of the interrupt enable bit. preiei is cleared to logic 0 when this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 215 register 020e: rhpp sts-1/stm-0 #1 path bip error counter bit type function default bit 15 r pbipe[15] x bit 14 r pbipe[14] x bit 13 r pbipe[13] x bit 12 r pbipe[12] x bit 11 r pbipe[11] x bit 10 r pbipe[10] x bit 9 r pbipe[9] x bit 8 r pbipe[8] x bit 7 r pbipe[7] x bit 6 r pbipe[6] x bit 5 r pbipe[5] x bit 4 r pbipe[4] x bit 3 r pbipe[3] x bit 2 r pbipe[2] x bit 1 r pbipe[1] x bit 0 r pbipe[0] x pbipe[15:0]: the path bip error (pbipe[15:0]) bits represent the number of path bip errors that have been detected in the b3 byte since the last accumulation interval. the error counters are transferred to the holding registers by a microprocessor write to this register or the suni- 2488 identity, and global performance monitor update register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 216 register 020f: rhpp sts-1/stm-0 #1 path rei error counter bit type function default bit 15 r preie[15] x bit 14 r preie[14] x bit 13 r preie[13] x bit 12 r preie[12] x bit 11 r preie[11] x bit 10 r preie[10] x bit 9 r preie[9] x bit 8 r preie[8] x bit 7 r preie[7] x bit 6 r preie[6] x bit 5 r preie[5] x bit 4 r preie[4] x bit 3 r preie[3] x bit 2 r preie[2] x bit 1 r preie[1] x bit 0 r preie[0] x preie[15:0]: the path rei error (preie[15:0]) bits represent the number of path rei errors that have been extracted from the g1 byte since the last accumulation interval. the error counters are transferred to the holding registers by a microprocessor write to this register or the suni- 2488 identity, and global performance monitor update register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 217 indirect register 00h: rhpp pointer interpreter configuration bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 unused bit 5 r/w ndfcnt 0 bit 4 r/w invcnt 0 bit 3 r/w relaypais 0 bit 2 r/w just3en 0 bit 1 r/w ssen 0 bit 0 r/w ptrcdis 0 ptrcdis: the concatenation pointer processing disable (ptrcdis) bit disables the path concatenation pointer interpreter state machine. when ptrcdis is set to logic 1, the path concatenation pointer interpreter state-machine is disabled and excluded from the lopc-p, aisc-p and allaisc-p defect declaration. when ptrcdis is set to logic 0, the path concatenation pointer interpreter state-machine is enabled and included in the lopc-p, aisc-p and allaisc-p defect declaration. this bit should be set to logic 1 for rhpp sts-1/stm0 #1 and logic 0 for all other rhpp sts-1/stm0 #n. ssen: the ss bits enable (ssen) bit selects whether or not the ss bits are taking into account in the pointer interpreter state machine. when ssen is set to logic 1, the ss bits must be set to 10 for a valid norm_point, ndf_enable, inc_ind, dec_ind or new_point indication. when ssen is set to logic 0, the ss bits are ignored. just3en: the ?justification more than 3 frames ago enable? (just3en) bit selects whether or not the ndf_enable, inc_ind or dec_ind pointer justifications must be more than 3 frames apart
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 218 to be considered valid. when just3en is set to logic 1, the previous ndf_enable, inc_ind or dec_ind indication must be more than 3 frames ago or the present ndf_enable, inc_ind or dec_ind indication is considered an inv_point indication. when just3en is set to logic 0, ndf_enable, inc_ind or dec_ind indication can be every frame. this bit is only valid for rhpp sts-1/stm0 #1. relaypais: the relay path ais (relaypais) bit selects the condition to enter the path ais state in the pointer interpreter state machine. when relaypais is set to logic 1, the path ais state is entered with 1 x ais_ind indication. when relaypais is set to logic 0, the path ais state is entered with 3 x ais_ind indications. this configuration bit also affects the concatenation pointer interpreter state machine. this bit is only valid for rhpp sts-1/stm0 #1. invcnt: the invalid counter (invcnt) bit selects the behavior of the consecutive inv_point event counter in the pointer interpreter state machine. when invcnt is set to logic 1, the consecutive inv_point event counter is reset by 3 x new_point indications. when invcnt is set to logic 0, the counter is not reset by 3 x new_point indications. this bit is only valid for rhpp sts-1/stm0 #1. ndfcnt: the new data flag counter (ndfcnt) bit selects the behavior of the consecutive ndf_enable event counter in the pointer interpreter state machine. when ndfcnt is set to logic 1, the ndf_enable definition is enabled ndf + ss. when ndfcnt is set to logic 0, the ndf_enable definition is enabled ndf + ss + offset value in the range 0 to 782 (764 in tu-3 mode). this configuration bit only changes the ndf_enable definition for the consecutive ndf_enable even counter to count towards lop-p defect when the pointer is out of range, this configuration bit does not change the ndf_enable definition for pointer justification. this bit is only valid for rhpp sts-1/stm0 #1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 219 indirect register 01h: rhpp error monitor configuration bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 r/w reserved 0 bit 11 r/w b3eonrpoh 0 bit 10 r/w ipreiblk 0 bit 9 r/w iber 0 bit 8 r/w preiblk 0 bit 7 r/w b3eblk 0 bit 6 r/w reserved 0 bit 5 r/w pbipblkacc 0 bit 4 r/w reserved 0 bit 3 r/w prdi10 0 bit 2 r/w plmend 0 bit 1 r/w psl5 0 bit 0 r/w algo2 0 algo2: the payload signal label algorithm 2 (algo2) bit selects the algorithm for the psl monitoring. when algo2 is set to logic 1, the itu compliant algorithm is (algorithm 2) is used to monitor the psl. when algo2 is set to logic 0, the bellcore compliant algorithm (algorithm 1) is used to monitor the psl. algo2 changes the plu-p, plm-p and pdi-p defect definitions but has no effect on uneq-p defect, accepted psl and change of psl definitions. this bit is only valid for rhpp sts-1/stm0 #1. psl5: the payload signal label detection (psl5) bit selects the path psl persistence. when psl5 is set to logic 1, a new psl is accepted when the same psl value is detected in the c2 byte for five consecutive frames. when psl5 is set to logic 0, a new psl is accepted when the same psl value is detected in the c2 byte for three consecutive frames. this bit is only valid for rhpp sts-1/stm0 #1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 220 plmend: the payload label mismatch removal (plmend) bit controls the removal of a plm-p defect when an uneq-p defect is declared. when plmend is set to logic 1, a plm-p defect is terminated when an uneq-p defect is declared. when plmend is set to logic 0, a plm-p defect is not terminated when an uneq-p defect is declared. this bit is only valid for rhpp sts-1/stm0 #1. prdi10: the path remote defect indication detection (prdi10) bit selects the path rdi and path erdi persistence. when prdi10 is set to logic 1, path rdi and path erdi are accepted when the same pattern is detected in bits 5,6,7 of the g1 byte for ten consecutive frames. when prdi10 is set to logic 0, path rdi and path erdi are accepted when the same pattern is detected in bits 5,6,7 of the g1 byte for five consecutive frames. this bit is only valid for rhpp sts-1/stm0 #1. pbipblkacc: the path block bip-8 errors accumulation (pbipblkacc) bit controls the accumulation of path bip-8 errors. when pbipblkacc is set to logic 1, the path bip-8 error accumulation represents block bip-8 errors (a maximum of 1 error per frame). when pbipblkacc is set to logic 0, the path bip-8 error accumulation represents bip-8 errors (a maximum of 8 errors per frame). this bit is only valid for rhpp sts-1/stm0 #1. b3eblk: the serial path block bip-8 errors (b3eblk) bit controls the indication of path bip-8 errors on the b3e serial output. when b3eblk is set to logic 1, b3e outputs block bip-8 errors (a maximum of 1 error per frame). when b3eblk is set to logic 0, b3e outputs bip-8 errors (a maximum of 8 errors per frame). this bit is only valid for rhpp sts-1/stm0 #1. preiblk: the path block rei errors (preiblk) bit controls the extraction of path rei errors from the path status (g1) byte. when preiblk is set to logic 1, the extracted path rei errors are interpreted as block bip-8 errors (a maximum of 1 error per frame). when preiblk is set to logic 0, the extracted path rei errors are interpret as bip-8 errors (a maximum of 8 errors per frame). this bit is only valid for rhpp sts-1/stm0 #1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 221 iber the inband error reporting (iber) bit controls the inband regeneration of the path status (g1) byte. when iber is set to logic 1, the path status byte is updated with the rei-p and the erdi-p defects that must be returned to the far end. when iber is set to logic 0, the path status byte is not altered. this bit is only valid for rhpp sts-1/stm0 #1. when operating as the protect mate, this bit should be set to logic 1. ipreiblk the inband path rei block errors (ipreiblk) bit controls the regeneration of the path rei errors in the path status (g1) byte. when ipreiblk is set to logic 1, the path rei is updated with block bip-8 errors (a maximum of 1 error per frame). when ipreiblk is set to logic 0, the path rei is updated with bip-8 errors (a maximum of 8 errors per frame). this bit is only valid for rhpp sts-1/stm0 #1. b3eonrpoh the b3e on rpoh bit controls whether the normal b3 output on rpoh should be replaced by the bip-8 error byte. when set to logic zero, b3 is output normally. when set to logic one, b3 in replaced by the bip-8 error code. this bit is only valid for rhpp sts-1/stm0 #1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 222 indirect register 02h: rhpp pointer value and erdi bit type function default bit 15 r perdiv[2] x bit 14 r perdiv[1] x bit 13 r perdiv[0] x bit 12 unused bit 11 r ssv[1] x bit 10 r ssv[0] x bit 9 r ptrv[9] x bit 8 r ptrv[8] x bit 7 r ptrv[7] x bit 6 r ptrv[6] x bit 5 r ptrv[5] x bit 4 r ptrv[4] x bit 3 r ptrv[3] x bit 2 r ptrv[2] x bit 1 r ptrv[1] x bit 0 r ptrv[0] x ptrv[9:0]: the path pointer value (ptrv[9:0]) bits represent the current sts (au or tu3) pointer being process by the pointer interpreter state machine or by the concatenation pointer interpreter state machine. ssv[1:0]: the ss value (ssv[1:0]) bits represent the current ss (dd) bits being processed by the pointer interpreter state machine or by the concatenation pointer interpreter state machine. perdiv[2:0]: the path enhanced remote defect indication value (perdiv[2:0]) bits represent the filtered path enhanced remote defect indication value. perdiv[2:0] is updated when the same erdi pattern is detected in bits 5,6,7 of the g1 byte for five or ten consecutive frames (selectable with the prdi10 register bit). these bits are only valid for rhpp sts-1/stm0 #1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 223 indirect register 03h: rhpp captured and accepted psl bit type function default bit 15 r cpslv[7] x bit 14 r cpslv[6] x bit 13 r cpslv[5] x bit 12 r cpslv[4] x bit 11 r cpslv[3] x bit 10 r cpslv[2] x bit 9 r cpslv[1] x bit 8 r cpslv[0] x bit 7 r apslv[7] x bit 6 r apslv[6] x bit 5 r apslv[5] x bit 4 r apslv[4] x bit 3 r apslv[3] x bit 2 r apslv[2] x bit 1 r apslv[1] x bit 0 r apslv[0] x this register is only used by the sts-1/stm-0 #1 slice. for all other slices, this register is invalid. apslv[7:0]: the accepted path signal label value (apslv[7:0]) bits represent the last accepted path signal label value. a new psl is accepted when the same psl value is detected in the c2 byte for three or five consecutive frames. (selectable with the psl5 register bit). algo2 register bit has no effect on apslv[7:0] cpslv[7:0]: the captured path signal label value (cpslv[7:0]) bits represent the last captured path signal label value. a new psl is captured every frame from the c2 byte.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 224 indirect register 04h: rhpp expected psl and pdi bit type function default bit 15 unused bit 14 unused bit 13 r/w pdirange 0 bit 12 r/w pdi[4] 0 bit 11 r/w pdi[3] 0 bit 10 r/w pdi[2] 0 bit 9 r/w pdi[1] 0 bit 8 r/w pdi[0] 0 bit 7 r/w epsl[7] 0 bit 6 r/w epsl[6] 0 bit 5 r/w epsl[5] 0 bit 4 r/w epsl[4] 0 bit 3 r/w epsl[3] 0 bit 2 r/w epsl[2] 0 bit 1 r/w epsl[1] 0 bit 0 r/w epsl[0] 0 this register is only used by the sts-1/stm-0 #1 slice. for all other slides, this register is invalid. epsl[7:0]: the expected path signal label (epsl[7:0]) bits represent the expected path signal label. the expected psl and the expected pdi validate the received or the accepted psl to declare plm-p, uneq-p and pdi-p defects according table 1. pdi[4:0], pdirange: the payload defect indication (pdi[4:0]) bits and the payload defect indication range (pdirange) bit determine the expected payload defect indication according to table 2. when pdirange is set to logic 1, the pdi range is enabled and the expected pdi range is from e1h to e0h+pdi[4:0]. when pdirange is set to logic 0, the pdi range is disable and the expected pdi value is e0h+pdi[4:0]. the expected psl and the expected pdi validate the received or the accepted psl to declare plm-p, uneq-p and pdi-p defects according table 1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 225 indirect register 05h: rhpp gpo and other status bit type function default bit 15 unused 0 bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 r ndf 0 bit 7 r illptr 0 bit 6 r invndf 0 bit 5 r discopa 0 bit 4 r concat 0 bit 3 r illjreq 0 bit 2 r newptr 0 bit 1 r/w reserved 0 bit 0 r/w reserved 0 newptr: the new pointer (newptr) signal is set high when an incoming pointer satisfying the new_point indication is received. this bit is only valid for rhpp sts-1/stm0 #1. illjreq: the illegal pointer justification request (illjreq) signal is set high when a positive and/or negative pointer adjustment is received within three frames of a pointer justification event (inc_ind, dec_ind) or an ndf triggered active offset adjustment (ndf_enable). this bit is only valid for rhpp sts-1/stm0 #1. concat: the concat bit is set high if the h1, h2 pointer byte received matches the concatenation indication (one of the five ndf_enable patterns in the ndf field, don't care in the size field, and all-ones in the pointer offset field).
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 226 discopa: the discontinuous change of pointer alignment (discopa) signal is set high when there is a pointer adjustment due to receiving a pointer repeated three times. this bit is only valid for rhpp sts-1/stm0 #1. invndf: the invalid new data flag (invndf) signal is set high when an invalid ndf code is received. this bit is only valid for rhpp sts-1/stm0 #1. illptr: the illegal pointer offset (illptr) signal is set high when the pointer received is out of the range. legal values are from 0 to 782 . pointer justification requests (inc_req, dec_req) and ais indications (ais_ind) are not considered illegal. this bit is only valid for rhpp sts-1/stm0 #1. ndf: the new data flag (ndf) signal is set high when an enabled new data flag is received indicating an pointer adjustment (ndf_enabled indication). this bit is only valid for rhpp sts-1/stm0 #1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 227 register 0400h: thpp sts-1/stm-0 #1 through #12 indirect address register 0480h: thpp sts-1/stm-0 #13 through #24 indirect address register 0500h: thpp sts-1/stm-0 #25 through #36 indirect address register 0580h: thpp sts-1/stm-0 #37 through #48 indirect address bit type function default bit 15 r busy x bit 14 r/w rwb 0 bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 r/w iaddr[3] 0 bit 7 r/w iaddr[2] 0 bit 6 r/w iaddr[1] 0 bit 5 r/w iaddr[0] 0 bit 4 unused bit 3 r/w path[3] 0 bit 2 r/w path[2] 0 bit 1 r/w path[1] 0 bit 0 r/w path[0] 0 path[3:0]: the sts-1/stm-0 path (path[3:0]) bits select which sts-1/stm-0 path is accessed by the current indirect transfer. path[3:0] sts-1/stm-0 path # 0000 invalid path 0001 path #(1, 13, 25 or 37) 0010 path #(2, 14, 26 or 38) 0011 path #(3, 15, 27 or 39) 0100 path #(4, 16, 28 or 40) 0101 path #(5, 17, 29 or 41) 0110 path #(6, 18, 30 or 42) 0111 path #(7, 19, 31 or 43) 1000 path #(8, 20, 32 or 44) 1001 path #(9, 21, 33 or 45) 1010 path #(10, 22, 34 or 46)
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 228 1011 path #(11, 23, 35 or47) 1100 path #(12, 24, 36 or 48) 1101- 1111 invalid path iaddr[3:0]: the address location (iaddr[3:0]) bits select which address location is accessed by the current indirect transfer. iaddr[3:0] indirect register 0000 thpp control register 0001 thpp source and pointer control 0010 thpp current pointer 0011 thpp arbitrary pointer 0100 thpp b3 mask and fixed stuff byte 0101 thpp transmit c2 and j1 0110 thpp transmit h4 mask and g1 0111 thpp transmit f2 and z3 1000 thpp transmit z4 and z5 1001 to 1111 unused rw b: the active high read and active low write (rwb) bit selects if the current access to a internal register is an indirect read or an indirect write. writing to the indirect address register initiates an access to a register. when rwb is set to logic 1, an indirect read access to a register is initiated. the data from the addressed location as indicated using the iaddr field will be transferred to the indirect data register. when rwb is set to logic 0, an indirect write access to a register is initiated. the data from the indirect data register will be transferred to the addressed register. busy: the active high busy (busy) bit reports if a previously initiated indirect access to an internal register has been completed. busy is set to logic 1 upon writing to the indirect address register. busy is set to logic 0, upon completion of the access. this register should be polled to determine when new data is available in the indirect data register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 229 register 0401h: thpp sts-1/stm-0 #1 through #12 indirect data register 0481h: thpp sts-1/stm-0 #13 through #24 indirect data register 0501h: thpp sts-1/stm-0 #25 through #36 indirect data register 0581h: thpp sts-1/stm-0 #37 through #48 indirect data bit type function default bit 15 r/w data[15] 0 bit 14 r/w data[14] 0 bit 13 r/w data[13] 0 bit 12 r/w data[12] 0 bit 11 r/w data[11] 0 bit 10 r/w data[10] 0 bit 9 r/w data[9] 0 bit 8 r/w data[8] 0 bit 7 r/w data[7] 0 bit 6 r/w data[6] 0 bit 5 r/w data[5] 0 bit 4 r/w data[4] 0 bit 3 r/w data[3] 0 bit 2 r/w data[2] 0 bit 1 r/w data[1] 0 bit 0 r/w data[0] 0 data[15:0]: the indirect access data (data[15:0]) bits hold the data transfer to or from an indirect register during indirect access. when rwb is set to logic 1 (indirect read), the data from the addressed location in the register will be transferred to data[15:0]. busy should be polled to determine when the new data is available in data[15:0]. when rwb is set to logic 0 (indirect write), the data from data[15:0] will be transferred to the register. the indirect data register must contain valid data before the indirect write is initiated by writing to the indirect address register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 230 register 0402: thpp payload configuration bit type function default bit 15 r/w reserved 0 bit 14 r/w reserved 0 bit 13 r/w reserved 0 bit 12 r/w fixptr 0 bit 11 r/w enesb 0 bit 10 unused bit 9 unused bit 8 unused bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w reserved 0
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 231 indirect register 00h: thpp control register bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 unused bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w fsben 0 bit 2 r/w preieblk 0 bit 1 r/w reserved 0 bit 0 r/w pais 0 pais: the pais bit controls the insertion of the path alarm indication signal. this register bit value is logically ored with the results form the sarc block. when a logic 1 is written to this bit position, the complete spe/vc-x, and the the pointer bytes (h1, h2) and stuffing opportunity bytes (h3) are overwritten with the all ones pattern. when a logic 0 is written to this bit position, the pointer bytes and the spe/vc-n are processed normally. upon de-activation of path ais, a new data flag accompanies the first valid pointer. this bit should be consistent for all thpp sts-1/stm0 #n. preieblk: the path rei block error (preieblk) bit controls the extraction of path rei errors in the prei monitoring block of the sts/au pointer. when preieblk is set to logic 1, the path rei extracted represents bip-8 block errors (a maximum of 1 error per frame). when preieblk is set to logic 0, the path rei extracted represents bip-8 errors (a maximum of 8 errors per frame). this bit is only valid for thpp sts-1/stm0 #1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 232 fsben: when the fsben register bit is logic one, thpp overwrites the fixed stuff byte . this bit should be consistent for all thpp sts-1/stm0 #1 through #48.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 233 indirect register 01h: thpp source and pointer control register bit type function default bit 15 0 bit 14 unused bit 13 r/w h4mask 0 bit 12 r/w b3mask 0 bit 11 r/w eng1rec 0 bit 10 r/w enh4mask 0 bit 9 r/w ptbj1 0 bit 8 r/w srcz5 0 bit 7 r/w srcz4 0 bit 6 r/w srcz3 0 bit 5 r/w srcf2 0 bit 4 r/w srcrei 0 bit 3 r/w srcrdi 0 bit 2 r/w srcc2 0 bit 1 r/w srcj1 0 bit 0 r/w iber 0 iber: when the iber register bit is set to logic one, the g1 byte is generated by the sirp block. the thpp overwrites the lsb of the pass-through g1 with a zero logic value. when iber is set to logic zero, the g1 byte can be modified by one of the piben: this bit is only valid for thpp sts-1/stm0 #1. srcj1, srcc2, srcf2, srcz3, srcz4, srcz5: the srcnn bits are used to determine the source for the path overhead bytes. for example, when a logic 1 is written to srcj1, the j1 byte inserted can be found in the thpp transmit c2 and j1 register. when a logic 0 is written to srcj1, the j1 byte source can either be the tpoh input or the tttp path depending on the value of the ptbj1 register bit that can be found in this register. these bits are only valid for thpp sts-1/stm0 #1. srcrei: the valid high srcrei register bit enables the thpp to overwrite the g1 byte with the rei field in the thpp transmit h4 mask and g1 register. when srcrei is set to logic zero, the rei source is other than the thpp transmit h4 mask and g1 register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 234 these bits are only valid for thpp sts-1/stm0 #1. srcrdi: the valid high srcrdi register bit enables the thpp to overwrite the g1 byte with the rdi field in the thpp transmit h4 mask and g1 register. when srcrei is set to logic zero, the rdi source is other than the thpp transmit h4 mask and g1 register. these bits are only valid for thpp sts-1/stm0 #1. ptbj1: the ptbj1 or path trace buffer j1 byte register bit is used to determine the origin of the path trace byte to be inserted. when ptbj1 is high, the j1 byte is sourced from the tttp path block; otherwise, the j1 byte is either sourced from the tpoh input or not inserted at all as controlled using the srcj1 bit. these bits are only valid for thpp sts-1/stm0 #1. enh4mask: when enh4mask is logic high, the h4[7:0] byte in thpp transmit h4 mask and g1 register is used as an error mask on the h4 byte. when enh4mask is logic low, the h4[7:0] byte in thpp transmit h4 mask and g1 register is inserted as the h4 byte. these bits are only valid for thpp sts-1/stm0 #1. eng1rec: the valid high eng1rec register bit enables the insertion of the prdi[2:0] and prei[3:0] of the g1 byte from the sarc block. when eng1rec is set to logic low, the g1 byte source is other than the sarc block. b3mask: when b3mask is logic high, the byte received via the tpoh (valid only if tpohen is logic high) bit serial stream is to be used as a mask for an internally generated b3. when b3mask is logic low, the byte received on tpoh (valid only if tpohen is logic high) will be inserted in the b3 byte if the path overhead source priority is tpoh. h4mask: when h4mask is logic high, the byte received via the tpoh (valid only if tpohen is logic high) bit serial stream is to be used as a mask for the h4 byte. when h4mask is logic low, the byte received on tpoh (valid only if tpohen is logic high) will be inserted in the h4 byte only if the path overhead source priority is tpoh.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 235 indirect register 02h: thpp current pointer register bit type function default bit 15 r ndf[3] 0 bit 14 r ndf[2] 0 bit 13 r ndf[1] 0 bit 12 r ndf[0] 0 bit 11 r s[1] 0 bit 10 r s[0] 0 bit 9 r cptr[9] 0 bit 8 r cptr[8] 0 bit 7 r cptr[7] 0 bit 6 r cptr[6] 0 bit 5 r cptr[5] 0 bit 4 r cptr[4] 0 bit 3 r cptr[3] 0 bit 2 r cptr[2] 0 bit 1 r cptr[1] 0 bit 0 r cptr[0] 0 cptr[9:0]: the cptr[9:0] bits in the thpp current pointer register reflect the value of the current payload pointer being inserted. this field can be used to verify the user programmable pointer when fixptr is logic one. s[1:0]: the s[1:0] bits in the thpp current pointer register reflect the ss bits being inserted. this field can be used by the to verify the ss field in the user programmable pointer when fixptr is logic one. ndf[3:0]: the ndf[3:0] bits in the thpp current pointer register reflect the ndf bit field being inserted. this field can be used to verify the ndf field in the user programmable pointer when fixptr is logic one.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 236 indirect register 03h: thpp arbitrary pointer register bit type function default bit 15 r/w ndf[3]/concat[15] 0 bit 14 r/w ndf[2]/concat[14] 0 bit 13 r/w ndf[1]/concat[13] 0 bit 12 r/w ndf[0]/concat[12] 0 bit 11 r/w s[1]/concat[11] 0 bit 10 r/w s[0]/concat[10] 0 bit 9 r/w aptr[9]/concat[9] 0 bit 8 r/w aptr[8]/concat[8] 0 bit 7 r/w aptr[7]/concat[7] 0 bit 6 r/w aptr[6]/concat[6] 0 bit 5 r/w aptr[5]/concat[5] 0 bit 4 r/w aptr[4]/concat[4] 0 bit 3 r/w aptr[3]/concat[3] 0 bit 2 r/w aptr[2]/concat[2] 0 bit 1 r/w aptr[1]/concat[1] 0 bit 0 r/w aptr[0]/concat[0] 0 aptr[9:0]: the aptr[9:0] bits are used to set an arbitrary payload pointer value. the arbitrary pointer value is transferred by writing a logic one to the pld bit in the thpp control register. a legal value (i.e. 0- 782) results in the thpp forcing a shifting to the corresponding byte position. if the ftptr bit is a logic 1, the current aptr[9:0] value is inserted into the payload pointer bytes (h1 and h2) continueously. these bits are only valid for thpp sts-1/stm0 #1. s[1:0]: the s[1:0] bits contain the value inserted in the s[1:0] bit positions in the payload pointer. these bits are only valid for thpp sts-1/stm0 #1. ndf[3:0]: the ndf[3:0] bits contain the value inserted in the ndf bit positions of a pointer. these bits are only valid for thpp sts-1/stm0 #1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 237 concat[15:0]: the concat[15:0] bits contain the value inserted in the h1 and h2 bit positions of a pointer. these bits are only valid for thpp sts-1/stm0 #2-#48.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 238 indirect register 05h: thpp b3 mask and fixed stuff byte bit type function default bit 15 r/w b3mask[7] 0 bit 14 r/w b3mask[6] 0 bit 13 r/w b3mask[5] 0 bit 12 r/w b3mask[4] 0 bit 11 r/w b3mask[3] 0 bit 10 r/w b3mask[2] 0 bit 9 r/w b3mask[1] 0 bit 8 r/w b3mask[0] 0 bit 7 r/w fsb[7] 0 bit 6 r/w fsb[6] 0 bit 5 r/w fsb[5] 0 bit 4 r/w fsb[4] 0 bit 3 r/w fsb[3] 0 bit 2 r/w fsb[2] 0 bit 1 r/w fsb[1] 0 bit 0 r/w fsb[0] 0 fsb[7:0]: when the fsben bit in the thpp control register is logic one, the thpp replaces the fixed bytes with the byte from this register. this field should be consistent for all thpp sts-1/stm0 #1 through #48. b3mask[7:0]: the calculated b3 parity byte is always xored with this register bit to allow the user to insert errors in b3. this field is only valid for thpp sts-1/stm0 #1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 239 indirect register 06h: thpp transmit c2 and j1 bit type function default bit 15 r/w c2[7] 0 bit 14 r/w c2[6] 0 bit 13 r/w c2[5] 0 bit 12 r/w c2[4] 0 bit 11 r/w c2[3] 0 bit 10 r/w c2[2] 0 bit 9 r/w c2[1] 0 bit 8 r/w c2[0] 0 bit 7 r/w j1[7] 0 bit 6 r/w j1[6] 0 bit 5 r/w j1[5] 0 bit 4 r/w j1[4] 0 bit 3 r/w j1[3] 0 bit 2 r/w j1[2] 0 bit 1 r/w j1[1] 0 bit 0 r/w j1[0] 0 j1[7:0]: the j1[7:0] bits are inserted in the j1 byte position when the srcj1 bit of the thpp source & pointer control register is logic 0 and tpohen is low during the path trace bit positions in the path overhead input stream, tpoh. this field is only valid for thpp sts-1/stm0 #1. c2[7:0]: the c2[7:0] bits are inserted in the c2 byte position when the srcc2 bit of the thpp source & pointer control register is logic 0 and tpohen is low during the path signal lable bit positions in the path overhead input stream, tpoh. this field is only valid for thpp sts-1/stm0 #1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 240 indirect register 07h: thpp transmit h4 mask and g1 bit type function default bit 15 r/w h4[7] 0 bit 14 r/w h4[6] 0 bit 13 r/w h4[5] 0 bit 12 r/w h4[4] 0 bit 11 r/w h4[3] 0 bit 10 r/w h4[2] 0 bit 9 r/w h4[1] 0 bit 8 r/w h4[0] 0 bit 7 r/w g1[7] 0 bit 6 r/w g1[6] 0 bit 5 r/w g1[5] 0 bit 4 r/w g1[4] 0 bit 3 r/w g1[3] 0 bit 2 r/w g1[2] 0 bit 1 r/w g1[1] 0 bit 0 r/w g1[0] 0 g1[7:0]: the g1[7:0] bits are inserted in the g1 byte position when the srcrei and srcrdi bits of the source and pointer control register are high and tpohen is low during the path status bit positions in the path overhead input stream, tpoh. this field is only valid for thpp sts-1/stm0 #1. h4[7:0]: the h4[7:0] bits are inserted in the h1 byte position when the enh4mask bit of the source and pointer control register is high and tpohen is low during the path multiframe bit positions in the path overhead input stream, tpoh. this field is only valid for thpp sts-1/stm0 #1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 241 indirect register 08h: thpp transmit f2 and z3 bit type function default bit 15 r/w f2[7] 0 bit 14 r/w f2[6] 0 bit 13 r/w f2[5] 0 bit 12 r/w f2[4] 0 bit 11 r/w f2[3] 0 bit 10 r/w f2[2] 0 bit 9 r/w f2[1] 0 bit 8 r/w f2[0] 0 bit 7 r/w z3[7] 0 bit 6 r/w z3[6] 0 bit 5 r/w z3[5] 0 bit 4 r/w z3[4] 0 bit 3 r/w z3[3] 0 bit 2 r/w z3[2] 0 bit 1 r/w z3[1] 0 bit 0 r/w z3[0] 0 z3[7:0]: the z3[7:0] bits are inserted in the z3 byte position when the srcz3 bit of the thpp source & pointer control register is logic 0 and input tpohen is low during the path z3 growth bit positions in the path overhead input stream, tpoh. this field is only valid for thpp sts-1/stm0 #1. f2[7:0]: the f2[7:0] bits are inserted in the f2 byte position when the srcf2 bit of the thpp source & pointer control register is logic 0 and input tpohen is low during the path user channel bit positions in the path overhead input stream, tpoh. this field is only valid for thpp sts-1/stm0 #1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 242 indirect register 09h: thpp transmit z4 and z5 bit type function default bit 15 r/w z4[7] 0 bit 14 r/w z4[6] 0 bit 13 r/w z4[5] 0 bit 12 r/w z4[4] 0 bit 11 r/w z4[3] 0 bit 10 r/w z4[2] 0 bit 9 r/w z4[1] 0 bit 8 r/w z4[0] 0 bit 7 r/w z5[7] 0 bit 6 r/w z5[6] 0 bit 5 r/w z5[5] 0 bit 4 r/w z5[4] 0 bit 3 r/w z5[3] 0 bit 2 r/w z5[2] 0 bit 1 r/w z5[1] 0 bit 0 r/w z5[0] 0 z5[7:0]: the z5[7:0] bits are inserted in the z5 byte position when the srcz5 bit of the thpp source & pointer control register is logic 0 and input tpohen is low during the path z5 growth bit positions in the path overhead input stream, tpoh. this field is only valid for thpp sts-1/stm0 #1. z4[7:0]: the z4[7:0] bits are inserted in the z4 byte position when the srcz4 bit of the thpp source & pointer control register is logic 0 and input tpohen is low during the path z4 growth bit positions in the path overhead input stream, tpoh. this field is only valid for thpp sts-1/stm0 #1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 243 register 0600h: rsvca indirect address bit type function default bit 15 r busy x bit 14 r/w rwb 0 bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 r/w iaddr[2] 0 bit 7 r/w iaddr[1] 0 bit 6 r/w iaddr[0] 0 bit 5 unused bit 4 unused bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w reserved 0 iaddr[2:0]: the address location (iaddr[2:0]) bits select which address location is accessed by the current indirect transfer. iaddr[2:0] indirect register 000 rsvca pointer justification interrupt enable 001 rsvca fifo interrupt enable 010 rsvca positive justification performance monitor 011 rsvca negative justification performance monitor 100 rsvca diagnostic/configuration 101 to 111 unused rw b: the active high read and active low write (rwb) bit selects if the current access to a internal register is an indirect read or an indirect write. writing to the indirect address register initiates an access to a register. when rwb is set to logic 1, an indirect read access to a register is initiated. the data from the addressed location as indicated using the iaddr field will be transferred to the indirect data register. when rwb is set to logic 0, an indirect write
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 244 access to a register is initiated. the data from the indirect data register will be transferred to the addressed register. busy: the active high busy (busy) bit reports if a previously initiated indirect access to an internal register has been completed. busy is set to logic 1 upon writing to the indirect address register. busy is set to logic 0, upon completion of the access. this register should be polled to determine when new data is available in the indirect data register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 245 register 0601h: rsvca indirect data bit type function default bit 15 r/w data[15] 0 bit 14 r/w data[14] 0 bit 13 r/w data[13] 0 bit 12 r/w data[12] 0 bit 11 r/w data[11] 0 bit 10 r/w data[10] 0 bit 9 r/w data[9] 0 bit 8 r/w data[8] 0 bit 7 r/w data[7] 0 bit 6 r/w data[6] 0 bit 5 r/w data[5] 0 bit 4 r/w data[4] 0 bit 3 r/w data[3] 0 bit 2 r/w data[2] 0 bit 1 r/w data[1] 0 bit 0 r/w data[0] 0 data[15:0]: the indirect access data (data[15:0]) bits hold the data transfer to or from an indirect register during indirect access. when rwb is set to logic 1 (indirect read), the data from the addressed location in the register will be transferred to data[15:0]. busy should be polled to determine when the new data is available in data[15:0]. when rwb is set to logic 0 (indirect write), the
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 246 data from data[15:0] will be transferred to the register. the indirect data register must contain
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 247
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 248 register 0603h: rsvca positive justification interrupt status bit type function default bit 15 r/w reserved[3] x bit 14 r/w reserved[2] x bit 13 r/w reserved[1] x bit 12 r/w reserved[0] x bit 11 r reserved 0 bit 10 r reserved 0 bit 9 r reserved 0 bit 8 r reserved 0 bit 7 r reserved 0 bit 6 r reserved 0 bit 5 r reserved 0 bit 4 r reserved 0 bit 3 r reserved 0 bit 2 r reserved 0 bit 1 r reserved 0 bit 0 r ppji[1] 0 ppji[1]: the positive pointer justification interrupt status (ppji[1]) bit indicates a positive pointer adjustment in the sts-48c/stm-4-4c stream. ppji[1] is set to logic 1 to indicate a positive pointer justification event in the outgoing data stream. this interrupt status bit is independent of the interrupt enable bit. ppji[1] is cleared to logic 0 when this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 249 register 0604h: rsvca negative justification interrupt status bit type function default bit 15 r/w reserved[3] x bit 14 r/w reserved[2] x bit 13 r/w reserved[1] x bit 12 r/w reserved[0] x bit 11 r reserved 0 bit 10 r reserved 0 bit 9 r reserved 0 bit 8 r reserved 0 bit 7 r reserved 0 bit 6 r reserved 0 bit 5 r reserved 0 bit 4 r reserved 0 bit 3 r reserved 0 bit 2 r reserved 0 bit 1 r reserved 0 bit 0 r npji[1] 0 npji[1]: the negative pointer justification interrupt status (npji[1]) bit indicates a negative pointer adjustment in the sts-48c/stm-4-4c stream. npji[1] is set to logic 1 to indicate a negative pointer justification event in the outgoing data stream. this interrupt status bit is independent of the interrupt enable bit. npji[1] is cleared to logic 0 when this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 250 register 0605h: rsvca fifo overflow interrupt status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r reserved 0 bit 10 r reserved 0 bit 9 r reserved 0 bit 8 r reserved 0 bit 7 r reserved 0 bit 6 r reserved 0 bit 5 r reserved 0 bit 4 r reserved 0 bit 3 r reserved 0 bit 2 r reserved 0 bit 1 r reserved 0 bit 0 r fovri[1] 0 fovri[1]: the fifo overflow event interrupt status (fovri[1]) bit indicates a fifo overflow in the svca. fovri[1] is set to logic 1 to indicate a fifo overflow event. this interrupt status bit is independent of the interrupt enable bit. fovri[1] is cleared to logic 0 when this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 251 register 0606h: rsvca fifo underflow interrupt status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r reserved 0 bit 10 r reserved 0 bit 9 r reserved 0 bit 8 r reserved 0 bit 7 r reserved 0 bit 6 r reserved 0 bit 5 r reserved 0 bit 4 r reserved 0 bit 3 r reserved 0 bit 2 r reserved 0 bit 1 r reserved 0 bit 0 r fudri[1] 0 fudri[1]: the fifo underflow event interrupt status (fudri[1]) bit indicates a fifo underflow in the svca. fudri[1] is set to logic 1 to indicate a fifo underflow event. this interrupt status bit is independent of the interrupt enable bit. fudri[1] is cleared to logic 0 when this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 252 indirect register 00h: rsvca pointer justification interrupt enable bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r/w reserved 0 bit 10 r/w reserved 0 bit 9 r/w reserved 0 bit 8 r/w reserved 0 bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w pjien[1] 0 pjien[1]: the pointer justification event interrupt enable (pjien[1]) bit controls the activation of the interrupt (intb) output. when set to logic 1, the corresponding pending interrupt will assert the interrupt (intb) output. when set to logic 0, the corresponding pending interrupt will not assert the interrupt (intb) output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 253 indirect register 01h: rsvca fifo interrupt enable bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r/w reserved 0 bit 10 r/w reserved 0 bit 9 r/w reserved 0 bit 8 r/w reserved 0 bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w fien[1] 0 fien[1]: the fifo event interrupt enable (fien[1]) bit controls the activation of the interrupt (intb) output due to a fifo overflow or a fifo underflow. when set to logic 1, the corresponding pending interrupts will assert the interrupt (intb) output. when set to logic 0, the corresponding pending interrupts will not assert the interrupt (intb) output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 254 indirect register 02h: rsvca positive justifications performance monitor bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 r pjpmon[12] 0 bit 11 r pjpmon[11] 0 bit 10 r pjpmon[10] 0 bit 9 r pjpmon[9] 0 bit 8 r pjpmon[8] 0 bit 7 r pjpmon[7] 0 bit 6 r pjpmon[6] 0 bit 5 r pjpmon[5] 0 bit 4 r pjpmon[4] 0 bit 3 r pjpmon[3] 0 bit 2 r pjpmon[2] 0 bit 1 r pjpmon[1] 0 bit 0 r pjpmon[0] 0 pjpmon[12:0]: this register reports the number of positive pointer justification events that occurred on the outgoing side in the previous accumulation interval. the content of this register becomes valid a maximum of 3 tclk cycles after a transfer is triggered by writing a logic one to the pmonxfer bit of the svca diagnostic/configuration register or by writing to the s/uni- 2488 identity, and global performance monitor update register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 255 indirect register 03h: rsvca negative justifications performance monitor bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 r njpmon[12] 0 bit 11 r njpmon[11] 0 bit 10 r njpmon[10] 0 bit 9 r njpmon[9] 0 bit 8 r njpmon[8] 0 bit 7 r njpmon[7] 0 bit 6 r njpmon[6] 0 bit 5 r njpmon[5] 0 bit 4 r njpmon[4] 0 bit 3 r njpmon[3] 0 bit 2 r njpmon[2] 0 bit 1 r njpmon[1] 0 bit 0 r njpmon[0] 0 njpmon[12:0]: this register reports the number of negative pointer justification events that occurred on the outgoing side in the previous accumulation interval. the content of this register becomes valid a maximum of 3 tclk cycles after a transfer is triggered by writing a logic one to the pmonxfer bit of the svca diagnostic/configuration register or by writing to the s/uni- 2488 identity, and global performance monitor update register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 256 indirect register 04h: rsvca diagnostic/configuration bit type function default bit 15 r/w reserved x bit 14 r/w ptr_rst x bit 13 w pmonxfer x bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused 0 bit 6 r/w reserved 0 bit 5 r/w diag_fifoaisdis 0 bit 4 r/w reserved 0 bit 3 r/w diag_pais 0 bit 2 r/w diag_lop 0 bit 1 r/w diag_negjust 0 bit 0 r/w diag_posjust 1 diag_posjust : the diag_posjust bit forces the svca to generate outgoing positive justification event. when set to 1, the svca generates positive justification events at the rate of one every four frames regardless of the current level of the internal fifo. prolonged application may cause the fifo to overflow. note : diag_posjust and diag_negjust must not be set to one at the same time. if that occurs, their operation is disabled. diag_negjust : the diag_negjust bit forces the svca to generate outgoing negative justification events. when set to 1, the svca generates negative justification events at the rate of one every four frames regardless of the current level of the internal fifo. prolonged application may cause the fifo to underflow. note : diag_posjust and diag_negjust must not be set to one at the same time. if that occurs, their operation is disabled. diag_lop : when set high, the diag_lop bit forces the svca to invert the outgoing ndf field of the payload (selected path(s)) pointer causing downstream pointer processing elements to enter a loss of pointer (lop) state.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 257 diag_pais : when set high, the diag_pais bit forces the svca to insert path ais in the selected outgoing stream for at least three consecutive frames. ais is inserted by writing an all ones pattern in the transport overhead bytes h1, h2, and h3, as well as in the entire sts synchronous payload envelope. the first frame after pais negates will contain a new data flag in the transport overhead h1 byte. diag_fifoaisdis : when set high, the diag_fifoaisdis bit forces the svca not to insert path ais upon fifo overflow/underflow detection. when set low (normal operation), detection of fifo overflow/underflow causes path ais to be inserted in the outgoing stream for at least three consecutive frames. pmon_xfer : when set high, negative and positive performance monitors are transferred to a stable readable register. ptr_rst: when set high, incoming and outgoing pointers are reset to their default values. this bit is level sensitive.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 258 register 0680h: tsvca indirect address bit type function default bit 15 r busy x bit 14 r/w rwb 0 bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 r/w iaddr[2] 0 bit 7 r/w iaddr[1] 0 bit 6 r/w iaddr[0] 0 bit 5 unused bit 4 unused bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w reserved 0 iaddr[2:0]: the address location (iaddr[2:0]) bits select which address location is accessed by the current indirect transfer. iaddr[2:0] indirect register 000 tsvca pointer justification interrupt enable 001 tsvca fifo interrupt enable 010 tsvca positive justification performance monitor 011 tsvca negative justification performance monitor 100 tsvca diagnostic/configuration 101 to 111 unused rw b: the active high read and active low write (rwb) bit selects if the current access to a internal register is an indirect read or an indirect write. writing to the indirect address register initiates an access to a register. when rwb is set to logic 1, an indirect read access to a register is initiated. the data from the addressed location as indicated using the iaddr field will be transferred to the indirect data register. when rwb is set to logic 0, an indirect write
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 259 access to a register is initiated. the data from the indirect data register will be transferred to the addressed register. busy: the active high busy (busy) bit reports if a previously initiated indirect access to an internal register has been completed. busy is set to logic 1 upon writing to the indirect address register. busy is set to logic 0, upon completion of the access. this register should be polled to determine when new data is available in the indirect data register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 260 register 0601h: tsvca indirect data bit type function default bit 15 r/w data[15] 0 bit 14 r/w data[14] 0 bit 13 r/w data[13] 0 bit 12 r/w data[12] 0 bit 11 r/w data[11] 0 bit 10 r/w data[10] 0 bit 9 r/w data[9] 0 bit 8 r/w data[8] 0 bit 7 r/w data[7] 0 bit 6 r/w data[6] 0 bit 5 r/w data[5] 0 bit 4 r/w data[4] 0 bit 3 r/w data[3] 0 bit 2 r/w data[2] 0 bit 1 r/w data[1] 0 bit 0 r/w data[0] 0 data[15:0]: the indirect access data (data[15:0]) bits hold the data transfer to or from an indirect register during indirect access. when rwb is set to logic 1 (indirect read), the data from the addressed location in the register will be transferred to data[15:0]. busy should be polled to determine when the new data is available in data[15:0]. when rwb is set to logic 0 (indirect write), the data from data[15:0] will be transferred to the register. the indirect data register must contain valid data before the indirect write is initiated by writing to the indirect address register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 261 register 0603h: tsvca positive justification interrupt status bit type function default bit 15 r/w reserved[3] x bit 14 r/w reserved[2] x bit 13 r/w reserved[1] x bit 12 r/w reserved[0] x bit 11 r reserved 0 bit 10 r reserved 0 bit 9 r reserved 0 bit 8 r reserved 0 bit 7 r reserved 0 bit 6 r reserved 0 bit 5 r reserved 0 bit 4 r reserved 0 bit 3 r reserved 0 bit 2 r reserved 0 bit 1 r reserved 0 bit 0 r ppji[1] 0 ppji[1]: the positive pointer justification interrupt status (ppji[1]) bit indicates a positive pointer adjustment in the sts-48c/stm-4-4c stream. ppji[1] is set to logic 1 to indicate a positive pointer justification event in the outgoing data stream. this interrupt status bit is independent of the interrupt enable bit. ppji[1] is cleared to logic 0 when this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 262 register 0604h: tsvca negative justification interrupt status bit type function default bit 15 r/w reserved[3] x bit 14 r/w reserved[2] x bit 13 r/w reserved[1] x bit 12 r/w reserved[0] x bit 11 r reserved 0 bit 10 r reserved 0 bit 9 r reserved 0 bit 8 r reserved 0 bit 7 r reserved 0 bit 6 r reserved 0 bit 5 r reserved 0 bit 4 r reserved 0 bit 3 r reserved 0 bit 2 r reserved 0 bit 1 r reserved 0 bit 0 r npji[1] 0 npji[1]: the negative pointer justification interrupt status (npji[1]) bit indicates a negative pointer adjustment in the sts-48c/stm-4-4c stream. npji[1] is set to logic 1 to indicate a negative pointer justification event in the outgoing data stream. this interrupt status bit is independent of the interrupt enable bit. npji[1] is cleared to logic 0 when this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 263 register 0605h: tsvca fifo overflow interrupt status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r reserved 0 bit 10 r reserved 0 bit 9 r reserved 0 bit 8 r reserved 0 bit 7 r reserved 0 bit 6 r reserved 0 bit 5 r reserved 0 bit 4 r reserved 0 bit 3 r reserved 0 bit 2 r reserved 0 bit 1 r reserved 0 bit 0 r fovri[1] 0 fovri[1]: the fifo overflow event interrupt status (fovri[1]) bit indicates a fifo overflow in the svca. fovri[1] is set to logic 1 to indicate a fifo overflow event. this interrupt status bit is independent of the interrupt enable bit. fovri[1] is cleared to logic 0 when this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 264 register 0606h: tsvca fifo underflow interrupt status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r reserved 0 bit 10 r reserved 0 bit 9 r reserved 0 bit 8 r reserved 0 bit 7 r reserved 0 bit 6 r reserved 0 bit 5 r reserved 0 bit 4 r reserved 0 bit 3 r reserved 0 bit 2 r reserved 0 bit 1 r reserved 0 bit 0 r fudri[1] 0 fudri[1]: the fifo underflow event interrupt status (fudri[1]) bit indicates a fifo underflow in the svca. fudri[1] is set to logic 1 to indicate a fifo underflow event. this interrupt status bit is independent of the interrupt enable bit. fudri[1] is cleared to logic 0 when this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 265 indirect register 00h: tsvca pointer justification interrupt enable bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r/w reserved 0 bit 10 r/w reserved 0 bit 9 r/w reserved 0 bit 8 r/w reserved 0 bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w pjien[1] 0 pjien[1]: the pointer justification event interrupt enable (pjien[1]) bit controls the activation of the interrupt (intb) output. when set to logic 1, the corresponding pending interrupt will assert the interrupt (intb) output. when set to logic 0, the corresponding pending interrupt will not assert the interrupt (intb) output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 266 indirect register 01h: tsvca fifo interrupt enable bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r/w reserved 0 bit 10 r/w reserved 0 bit 9 r/w reserved 0 bit 8 r/w reserved 0 bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w fien[1] 0 fien[1]: the fifo event interrupt enable (fien[1]) bit controls the activation of the interrupt (intb) output due to a fifo overflow or a fifo underflow. when set to logic 1, the corresponding pending interrupts will assert the interrupt (intb) output. when set to logic 0, the corresponding pending interrupts will not assert the interrupt (intb) output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 267 indirect register 02h: tsvca positive justifications performance monitor bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 r pjpmon[12] 0 bit 11 r pjpmon[11] 0 bit 10 r pjpmon[10] 0 bit 9 r pjpmon[9] 0 bit 8 r pjpmon[8] 0 bit 7 r pjpmon[7] 0 bit 6 r pjpmon[6] 0 bit 5 r pjpmon[5] 0 bit 4 r pjpmon[4] 0 bit 3 r pjpmon[3] 0 bit 2 r pjpmon[2] 0 bit 1 r pjpmon[1] 0 bit 0 r pjpmon[0] 0 pjpmon[12:0]: this register reports the number of positive pointer justification events that occurred on the outgoing side in the previous accumulation interval. the content of this register becomes valid a maximum of 3 tclk cycles after a transfer is triggered by writing a logic one to the pmonxfer bit of the svca diagnostic/configuration register or by writing to the s/uni- 2488 identity, and global performance monitor update register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 268 indirect register 03h: tsvca negative justifications performance monitor bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 r njpmon[12] 0 bit 11 r njpmon[11] 0 bit 10 r njpmon[10] 0 bit 9 r njpmon[9] 0 bit 8 r njpmon[8] 0 bit 7 r njpmon[7] 0 bit 6 r njpmon[6] 0 bit 5 r njpmon[5] 0 bit 4 r njpmon[4] 0 bit 3 r njpmon[3] 0 bit 2 r njpmon[2] 0 bit 1 r njpmon[1] 0 bit 0 r njpmon[0] 0 njpmon[12:0]: this register reports the number of negative pointer justification events that occurred on the outgoing side in the previous accumulation interval. the content of this register becomes valid a maximum of 3 tclk cycles after a transfer is triggered by writing a logic one to the pmonxfer bit of the svca diagnostic/configuration register or by writing to the s/uni- 2488 identity, and global performance monitor update register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 269 indirect register 04h: tsvca diagnostic/configuration bit type function default bit 15 r/w reserved x bit 14 r/w ptr_rst x bit 13 w pmonxfer x bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused 0 bit 6 r/w reserved 0 bit 5 r/w diag_fifoaisdis 0 bit 4 r/w reserved 0 bit 3 r/w diag_pais 0 bit 2 r/w diag_lop 0 bit 1 r/w diag_negjust 0 bit 0 r/w diag_posjust 1 diag_posjust : the diag_posjust bit forces the svca to generate outgoing positive justification event. when set to 1, the svca generates positive justification events at the rate of one every four frames regardless of the current level of the internal fifo. prolonged application may cause the fifo to overflow. note : diag_posjust and diag_negjust must not be set to one at the same time. if that occurs, their operation is disabled. diag_negjust : the diag_negjust bit forces the svca to generate outgoing negative justification events. when set to 1, the svca generates negative justification events at the rate of one every four frames regardless of the current level of the internal fifo. prolonged application may cause the fifo to underflow. note : diag_posjust and diag_negjust must not be set to one at the same time. if that occurs, their operation is disabled. diag_lop : when set high, the diag_lop bit forces the svca to invert the outgoing ndf field of the payload (selected path(s)) pointer causing downstream pointer processing elements to enter a loss of pointer (lop) state.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 270 diag_pais : when set high, the diag_pais bit forces the svca to insert path ais in the selected outgoing stream for at least three consecutive frames. ais is inserted by writing an all ones pattern in the transport overhead bytes h1, h2, and h3, as well as in the entire sts synchronous payload envelope. the first frame after pais negates will contain a new data flag in the transport overhead h1 byte. diag_fifoaisdis : when set high, the diag_fifoaisdis bit forces the svca not to insert path ais upon fifo overflow/underflow detection. when set low (normal operation), detection of fifo overflow/underflow causes path ais to be inserted in the outgoing stream for at least three consecutive frames. pmon_xfer : when set high, negative and positive performance monitors are transferred to a stable readable register. ptr_rst: when set high, incoming and outgoing pointers are reset to their default values. this bit is level sensitive.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 271 register 0700h: rttp path indirect address bit type function default bit 15 r busy x bit 14 r/w rwb 0 bit 13 r/w iaddr[7] 0 bit 12 r/w iaddr[6] 0 bit 11 r/w iaddr[5] 0 bit 10 r/w iaddr[4] 0 bit 9 r/w iaddr[3] 0 bit 8 r/w iaddr[2] 0 bit 7 r/w iaddr[1] 0 bit 6 r/w iaddr[0] 0 bit 5 unused bit 4 unused bit 3 r/w path[3] 0 bit 2 r/w path[2] 0 bit 1 r/w path[1] 0 bit 0 r/w path[0] 0 path[3:0]: the sts-1/stm-0 path (path[3:0]) bits select which sts-1/stm-0 path is accessed by the current indirect transfer. this register should only be set to 0001 since only the sts-1/stm-0 #1 path byte is valid.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 272 iaddr[7:0]: the indirect address location (iaddr[7:0]) bits select which indirect address location is accessed by the current indirect transfer. indirect address iaddr[7:0] indirect data 0000 0000 configuration 0000 0001 to 0011 1111 invalid address 0100 0000 first byte of the 1/16/64 byte captured trace 0100 0001 to 0111 1111 other bytes of the 16/64 byte captured trace 1000 0000 first byte of the 1/16/64 byte accepted trace 1000 0001 to 1011 1111 other bytes of the 16/64 byte accepted trace 1100 0000 first byte of the 16/64 byte expected trace 1100 0001 to 1111 1111 other bytes of the 16/64 byte expected trace rw b: the active high read and active low write (rwb) bit selects if the current access to the internal ram is an indirect read or an indirect write. writing to the indirect address register initiates an access to the internal ram. when rwb is set to logic 1, an indirect read access to the ram is initiated. the data from the addressed location in the internal ram will be transferred to the indirect data register. when rwb is set to logic 0, an indirect write access to the ram is initiated. the data from the indirect data register will be transferred to the addressed location in the internal ram. busy: the active high ram busy (busy) bit reports if a previously initiated indirect access to the internal ram has been completed. busy is set to logic 1 upon writing to the indirect address register. busy is set to logic 0, upon completion of the ram access. this register should be polled to determine when new data is available in the indirect data register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 273 register 0701h: rttp path indirect data bit type function default bit 15 r/w data[15] 0 bit 14 r/w data[14] 0 bit 13 r/w data[13] 0 bit 12 r/w data[12] 0 bit 11 r/w data[11] 0 bit 10 r/w data[10] 0 bit 9 r/w data[9] 0 bit 8 r/w data[8] 0 bit 7 r/w data[7] 0 bit 6 r/w data[6] 0 bit 5 r/w data[5] 0 bit 4 r/w data[4] 0 bit 3 r/w data[3] 0 bit 2 r/w data[2] 0 bit 1 r/w data[1] 0 bit 0 r/w data[0] 0 data[15:0]: the indirect access data (data[15:0]) bits hold the data transfer to or from the internal ram during indirect access. when rwb is set to logic 1 (indirect read), the data from the addressed location in the internal ram will be transfer to data[15:0]. busy should be polled to determine when the new data is available in data[15:0]. when rwb is set to logic 0 (indirect write), the data from data[15:0] will be transfer to the addressed location in the internal ram. the indirect data register must contain valid data before the indirect write is initiated by writing to the indirect address register. data[15:0] has a different meaning depending on which address of the internal ram is being accessed.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 274 register 0702h: rttp path trace unstable status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r reserve x bit 10 r reserve x bit 9 r reserve x bit 8 r reserve x bit 7 r reserve x bit 6 r reserve x bit 5 r reserve x bit 4 r reserve x bit 3 r reserve x bit 2 r reserve x bit 1 r reserve x bit 0 r tiuv[1] x tiuv[1]: the trace identifier unstable status (tiuv[1]) bit indicates the current status of the tiu defect. algorithm 1: tiuv is set to logic 0. algorithm 2: tiuv is set to logic 1 when one or more erroneous bytes are detected between the current message and the previous message in a total of 8 tail trace messages without any persistent message in between. tiuv is set to logic 0 when a persistent message is found. a persistent message is found when the same message is receive for 3 or 5 consecutive multi-frames. algorithm 3: tiuv is set to logic 1 when one or more erroneous bytes are detected in three consecutive sixteen byte windows. the first window starts on the first erroneous tail trace byte. byte_tiuv is set to logic 0 when the same tail trace byte is received for 48 consecutive frames.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 275 register 0703h: rttp path trace unstable interrupt enable bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r/w reserve 0 bit 10 r/w reserve 0 bit 9 r/w reserve 0 bit 8 r/w reserve 0 bit 7 r/w reserve 0 bit 6 r/w reserve 0 bit 5 r/w reserve 0 bit 4 r/w reserve 0 bit 3 r/w reserve 0 bit 2 r/w reserve 0 bit 1 r/w reserve 0 bit 0 r/w tiue[1] 0 tiue[1]: the trace identifier unstable interrupt enable (tiue[1]) bit controls the activation of the interrupt (intb) output. when the bit is set to logic 1, the corresponding pending interrupt will assert the interrupt (intb) output. when the bit is set to logic 0, the corresponding pending interrupt will not assert the interrupt (intb) output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 276 register 0704h: rttp path trace unstable interrupt status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r reserve x bit 10 r reserve x bit 9 r reserve x bit 8 r reserve x bit 7 r reserve x bit 6 r reserve x bit 5 r reserve x bit 4 r reserve x bit 3 r reserve x bit 2 r reserve x bit 1 r reserve x bit 0 r tiui[1] x tiui[1]: the trace identifier unstable interrupt status (tiui[1]) bit is an event indicator. tiui[1] is set to logic 1 to indicate any changes in the status of tiuv[1] (stable to unstable, unstable to stable). this interrupt status bit is independent of the interrupt enable bit. tiui[1] is cleared to logic 0 when this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 277 register 0705h: rttp path trace mismatch status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r reserve x bit 10 r reserve x bit 9 r reserve x bit 8 r reserve x bit 7 r reserve x bit 6 r reserve x bit 5 r reserve x bit 4 r reserve x bit 3 r reserve x bit 2 r reserve x bit 1 r reserve x bit 0 r timv[1] x timv[1]: the trace identifier mismatch status (timv[1]) bit indicates the current status of the tim defect. algorithm 1: timv is set to logic 1 when none of the last 20 messages matches the expected message. timv is set to logic 0 when 16 of the last 20 messages match the expected message. algorithm 2: timv is set to logic 1 when the accepted message does not match the expected message. timv is set to logic 0 when the accepted message matches the expected message. algorithm 3: timv is set to logic 0.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 278 register 0706h: rttp path trace mismatch interrupt enable bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r/w reserve 0 bit 10 r/w reserve 0 bit 9 r/w reserve 0 bit 8 r/w reserve 0 bit 7 r/w reserve 0 bit 6 r/w reserve 0 bit 5 r/w reserve 0 bit 4 r/w reserve 0 bit 3 r/w reserve 0 bit 2 r/w reserve 0 bit 1 r/w reserve 0 bit 0 r/w time[1] 0 time[1]: the trace identifier mismatch interrupt enable (time[1]) bit controls the activation of the interrupt (intb) output. when set to logic 1, the corresponding pending interrupt will assert the interrupt (intb) output. when set to logic 0, the corresponding pending interrupt will not assert the interrupt (intb) output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 279 register 0707h: rttp path trace mismatch interrupt status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r reserve x bit 10 r reserve x bit 9 r reserve x bit 8 r reserve x bit 7 r reserve x bit 6 r reserve x bit 5 r reserve x bit 4 r reserve x bit 3 r reserve x bit 2 r reserve x bit 1 r reserve x bit 0 r timi[1] x timi[1]: the trace identifier mismatch interrupt status (timi[1]) bit is an event indicator. timi[1] is set to logic 1 to indicate any changes in the status of timv[1] (match to mismatch, mismatch to match). this interrupt status bit is independent of the interrupt enable bit. timi[1] is cleared to logic 0 when this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 280 indirect register 00h: rttp path trace configuration bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 unused bit 5 r/w zeroen 0 bit 4 r/w per5 0 bit 3 r/w nosync 0 bit 2 r/w length16 0 bit 1 r/w algo[1] 0 bit 0 r/w algo[0] 0 algo[1:0]: the tail trace algorithm select (algo[1:0]) bits select the algorithm used to process the tail trace message. algo[1:0] tail trace algorithm 00 algorithm disable 01 algorithm 1 10 algorithm 2 11 algorithm 3 when algo[1:0] is set to logic 00b, the tail trace algorithms are disable. the corresponding tiuv, timv register bits and the corresponding tiu, tim output signal time slots are set to logic 0. length16: the message length (length16) bit selects the length of the tail trace message use by algorithm 1 and algorithm 2. when length16 is set to logic 1, the length of the tail trace message is 16 byte. when length16 is set to logic 0, the length of the tail trace message is 64 byte.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 281 nosync: the synchronization disable (nosync) bit disables the synchronization of the tail trace message in algorithm 1 and algorithm 2. when nosync is set to logic 1, no synchronization is done on the tail trace message. the bytes of the tail trace message are written in the captured page as in a circular buffer. when nosync is set to logic 0, synchronization is done on the tail trace message. when length16 is set to logic 1, the tail trace message is synchronize on the msb of the tail trace message. the byte with its msb set high is placed in the first byte location of the captured page. when length16 is set to logic 0, the tail trace message is synchronize on the cr/lf (cr = 0dh, lf = 0ah) characters of the tail trace message. the byte following the cr/lf bytes is placed in the first byte location of the captured page. per5: the message persistency (per5) bit selects the number of multi-frames a tail trace message must be received in order to be declared persistent in algorithm 2. when per5 is set to logic 1, the same tail trace message must be receive for 5 consecutive multi-frames to be declared persistent. when per5 is set to logic 0, the same tail trace message must be received for 3 consecutive multi frame to be declared persistent. zeroen: the all zero message enable (zeroen) bit selects if the all zero message are validated or not against the expected message in algorithm 1 and algorithm 2. when zeroen is set to logic 1, an all zero captured message in algorithm 1 and an all zero accepted message in algorithm 2 are validated against the expected message. a match is declared when both the captured/accepted message and the expected message are all zero. when zeroen is set to logic 0, an all zero captured message in algorithm 1 and an all zero accepted message in algorithm 2 are not validated against the expected message but are considered match. a match is declared when the captured/accepted message is all zero regardless of the expected message.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 282 indirect register 40h to 7fh: rttp path captured trace bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 r/w ctrace[7] x bit 6 r/w ctrace[6] x bit 5 r/w ctrace[5] x bit 4 r/w ctrace[4] x bit 3 r/w ctrace[3] x bit 2 r/w ctrace[2] x bit 1 r/w ctrace[1] x bit 0 r/w ctrace[0] x the rttp path captured trace indirect register is provided at rttp r/w indirect address 40h to 7fh. ctrace[7:0]: the captured tail trace message (ctrace[7:0]) bits contain the currently received tail trace message. when algorithm 1 or 2 is selected and length16 is set to logic 1, the captured message is stored between address 40h and 4fh. when algorithm 1 or 2 is selected and length16 is set to logic 0, the captured message is stored between address 40h and 7fh. when nosync is set to logic 1, the captured message is not synchronize. when nosync is set to logic 0, the captured message is synchronized and the first byte of the message is stored at address 40h. when algorithm 3 is selected, the captured byte is stored at address 40h.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 283 indirect register 80h to bfh: rttp path accepted trace bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 r/w atrace[7] x bit 6 r/w atrace[6] x bit 5 r/w atrace[5] x bit 4 r/w atrace[4] x bit 3 r/w atrace[3] x bit 2 r/w atrace[2] x bit 1 r/w atrace[1] x bit 0 r/w atrace[0] x the rttp path accepted trace indirect register is provided at rttp r/w indirect address 80h to bfh. atrace[7:0]: the accepted tail trace message (atrace[7:0]) bits contain the persistent tail trace message. when algorithm 2 is selected and per5 is set to logic 1, the accepted message is the same tail trace message received for 5 consecutive multi-frames. when algorithm 2 is selected and per5 is set to logic 0, the accepted message is the same tail trace message received for 3 consecutive multi-frames. when algorithm 2 is selected and length16 is set to logic 1, the accepted message is stored between address 80h and 8fh. when algorithm 2 is selected and length16 is set to logic 0, the accepted message is stored between address 80h and bfh. when algorithm 3 is selected, the accepted byte is the same tail trace byte received for 48 frames. when algorithm 3 is selected, the accepted byte is stored at address 80h.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 284 indirect register c0h to ffh: rttp path expected trace bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 r/w etrace[7] x bit 6 r/w etrace[6] x bit 5 r/w etrace[5] x bit 4 r/w etrace[4] x bit 3 r/w etrace[3] x bit 2 r/w etrace[2] x bit 1 r/w etrace[1] x bit 0 r/w etrace[0] x the rttp path expected trace indirect register is provided at rttp r/w indirect address c0h to ffh. etrace[7:0]: the expected tail trace message (etrace[7:0]) bits contain a static message written by an external microprocessor. in algorithm 1 the expected message is used to validated the captured message. in algorithm 2 the expected message is used to validate the accepted message. when length16 is set to logic 1, the expected message must be written between address c0h and cfh. when length16 is set to logic 0, the accepted message must be written between address c0h and ffh.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 285 register 0708h: tttp path indirect address bit type function default bit 15 r busy x bit 14 r/w rwb 0 bit 13 unused bit 12 r/w iaddr[6] 0 bit 11 r/w iaddr[5] 0 bit 10 r/w iaddr[4] 0 bit 9 r/w iaddr[3] 0 bit 8 r/w iaddr[2] 0 bit 7 r/w iaddr[1] 0 bit 6 r/w iaddr[0] 0 bit 5 unused bit 4 unused bit 3 r/w path[3] 0 bit 2 r/w path[2] 0 bit 1 r/w path[1] 0 bit 0 r/w path[0] 0 path[3:0]: the sts-1/stm-0 path (path[3:0]) bits select which sts-1/stm-0 path is accessed by the current indirect transfer. path[3:0] should be set to 0001.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 286 iaddr[6:0]: the indirect address location (iaddr[6:0]) bits select which indirect address location is accessed by the current indirect transfer. indirect address iaddr[6:0] indirect data 000 0000 configuration 000 0001 to 011 1111 invalid address 100 0000 first byte of the 1/16/64 byte trace 100 0001 to 111 1111 other bytes of the 16/64 byte trace rw b: the active high read and active low write (rwb) bit selects if the current access to the internal ram is an indirect read or an indirect write. writing to the indirect address register initiates an access to the internal ram. when rwb is set to logic 1, an indirect read access to the ram is initiated. the data from the addressed location in the internal ram will be transferred to the indirect data register. when rwb is set to logic 0, an indirect write access to the ram is initiated. the data from the indirect data register will be transferred to the addressed location in the internal ram. busy: the active high ram busy (busy) bit reports if a previously initiated indirect access to the internal ram has been completed. busy is set to logic 1 upon writing to the indirect address register. busy is set to logic 0, upon completion of the ram access. this register should be polled to determine when new data is available in the indirect data register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 287 register 0709h: tttp path indirect data bit type function default bit 15 r/w data[15] 0 bit 14 r/w data[14] 0 bit 13 r/w data[13] 0 bit 12 r/w data[12] 0 bit 11 r/w data[11] 0 bit 10 r/w data[10] 0 bit 9 r/w data[9] 0 bit 8 r/w data[8] 0 bit 7 r/w data[7] 0 bit 6 r/w data[6] 0 bit 5 r/w data[5] 0 bit 4 r/w data[4] 0 bit 3 r/w data[3] 0 bit 2 r/w data[2] 0 bit 1 r/w data[1] 0 bit 0 r/w data[0] 0 data[15:0]: the indirect access data (data[15:0]) bits hold the data transfer to or from the internal ram during indirect access. when rwb is set to logic 1 (indirect read), the data from the addressed location in the internal ram will be transfer to data[15:0]. busy should be polled to determine when the new data is available in data[15:0]. when rwb is set to logic 0 (indirect write), the data from data[15:0] will be transferred to the addressed location in the internal ram. the indirect data register must contain valid data before the indirect write is initiated by writing to the indirect address register. data[15:0] has a different meaning depending on which address of the internal ram is being accessed.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 288 indirect register 00h: tttp path trace configuration bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 unused bit 5 unused bit 4 unused bit 3 unused bit 2 r/w zeroen 0 bit 1 r/w byteen 0 bit 0 r/w length16 0 length16: the message length (length16) bit selects the length of the tail trace message to be transmitted. when length16 is set to logic 1, the length of the tail trace message is 16 byte. when length16 is set to logic 0, the length of the tail trace message is 64 byte. byteen: the single byte message enable (byteen) bit enables the single byte tail trace message. when byteen is set to logic 1, the length of the tail trace message is 1 byte. when byteen is set to logic 0, the length of the tail trace message is determined by length16. byteen has precedence over length16. zeroen: the all zero message enable (zeroen) bit enables the transmission of an all zero tail trace message. when zeroen is set to logic 1, an all zero message is transmitted. when zeroen is set to logic 0, the ram message is transmitted. the enabling and disabling of the all zero tail trace message is not done on message boundary since the receiver is required to perform filtering on the message.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 289 indirect register 40h to 7fh: tttp path trace bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 r/w trace[7] x bit 6 r/w trace[6] x bit 5 r/w trace[5] x bit 4 r/w trace[4] x bit 3 r/w trace[3] x bit 2 r/w trace[2] x bit 1 r/w trace[1] x bit 0 r/w trace[0] x trace[7:0]: the tail trace message (trace[7:0]) bits contain the tail trace message to be transmitted. when byteen is set to logic 1, the message is stored at indirect register address 40h. when byteen is set to logic 0 and length16 is set to logic 1, the message is stored between indirect register address 40h and 4fh. when byteen is set to logic 0 and length16 is set to logic 0, the message is stored between indirect register address 40h and 7fh.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 290 register 0720h: sarc indirect address bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 unused bit 5 unused bit 4 unused bit 3 r/w path[3] 0 bit 2 r/w path[2] 0 bit 1 r/w path[1] 0 bit 0 r/w path[0] 0 path[3:0]: this field should be set ot 1h
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 291 register 0722h: sarc section configuration bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 unused bit 6 unused bit 5 unused bit 4 unused bit 3 unused bit 2 unused bit 1 r/w lrdi22 0 bit 0 r/w reserved 0 lrdi22: the line remote defect indication (lrdi22) bit selects the line rdi persistence when line rdi is asserted as a result of received defects. when lrdi22 is set to logic 1, a new line rdi-l indication is transmitted for at least 22 frames. when lrdi22 is set to logic 0, a new line rdi indication is transmitted for at least 12 frames.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 292 register 0723h: sarc section salm enable bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r/w growth[1] 0 bit 10 r/w growth[0] 0 bit 9 r/w sfberen 0 bit 8 r/w sdberen 0 bit 7 r/w stimen 0 bit 6 r/w stiuen 0 bit 5 r/w apsbfen 0 bit 4 r/w lrdien 0 bit 3 r/w laisen 0 bit 2 r/w losen 0 bit 1 r/w lofen 0 bit 0 r/w oofen 0 oofen: the oof enable bit allows the out of frame defect to be ored into the salm output. when the oofen bit is set high, the corresponding defect indication is ored with other defect indications and output on salm. when the oofen bit is set low, the corresponding defect indication does not affect the salm output. lofen: the lof enable bit allows the loss of frame defect to be ored into the salm output. when the lofen bit is set high, the corresponding defect indication is ored with other defect indications and output on salm. when the lofen bit is set low, the corresponding defect indication does not affect the salm output. losen: the los enable bit allows the loss of signal defect to be ored into the salm output. when the losen bit is set high, the corresponding defect indication is ored with other defect indications and output on salm. when the losen bit is set low, the corresponding defect indication does not affect the salm output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 293 laisen: the lais enable bit allows the line alarm indication signal defect to be ored into the salm output. when the laisen bit is set high, the corresponding defect indication is ored with other defect indications and output on salm. when the laisen bit is set low, the corresponding defect indication does not affect the salm output. lrdien: the lrdi enable bit allows the line remote defect indication defect to be ored into the salm output. when the lrdien bit is set high, the corresponding defect indication is ored with other defect indications and output on salm. when the lrdien bit is set low, the corresponding defect indication does not affect the salm output. apsbfen: the apsbf enable bit allows the aps byte failure defect to be ored into the salm output. when the apsbfen bit is set high, the corresponding defect indication is ored with other defect indications and output on salm. when the apsbfen bit is set low, the corresponding defect indication does not affect the salm output. stiuen: the stiu enable bit allows the section trace identifier unstable defect to be ored into the salm output. when the stiuen bit is set high, the corresponding defect indication is ored with other defect indications and output on salm. when the stiuen bit is set low, the corresponding defect indication does not affect the salm output. stimen: the stim enable bit allows the section trace identifier mismatch defect to be ored into the salm output. when the stimen bit is set high, the corresponding defect indication is ored with other defect indications and output on salm. when the stimen bit is set low, the corresponding defect indication does not affect the salm output. sdberen: the sdber enable bit allows the signal degrade ber defect to be ored into the salm output. when the sdberen bit is set high, the corresponding defect indication is ored with other defect indications and output on salm. when the sdberen bit is set low, the corresponding defect indication does not affect the salm output. sfberen: the sfber enable bit allows the signal failure ber defect to be ored into the salm output. when the sfberen bit is set high, the corresponding defect indication is ored with other defect indications and output on salm. when the sfberen bit is set low, the corresponding defect indication does not affect the salm output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 294 growthen[1:0]: the growth enable bit allows the growth defect to be ored into the salm output. when the growthen bit is set high, the corresponding defect indication is ored with other defect indications and output on salm. when the growthen bit is set low, the corresponding defect indication does not affect the salm output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 295 register 0724h: sarc section rlaisins enable bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r/w growth[1] 0 bit 10 r/w growth[0] 0 bit 9 r/w sfberen 0 bit 8 r/w sdberen 0 bit 7 r/w stimen 0 bit 6 r/w stiuen 0 bit 5 r/w apsbfen 0 bit 4 r/w lrdien 0 bit 3 r/w laisen 0 bit 2 r/w losen 0 bit 1 r/w lofen 0 bit 0 r/w oofen 0 oofen, lofen, losen, laisen, lrdien, apsbfen, stiuen, stimen, sdberen, sfberen, growthen[1:0]: the above enable bits allows for the auto assertion of receive lais based on the following conditions: - out of frame defect - loss of frame defect - loss of signal defect - line alarm indication signal defect - line remote defect indication defect - aps byte failure defect - section trace identifier unstable defect - section trace identifier mismatch defect - signal degrade ber defect - signal failure ber defect - growth defect when the bit is set high, the corresponding defect indication is ored with other defect indications and the result forces receive lais. under receive lais, a all ones pattern is written into the receive line overhead and spe bytes. when the bit is set low, the corresponding defect indication does not affect the assertion of receive lais.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 296 register 0725h: sarc section tlrdiins enable bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r/w growth[1] 0 bit 10 r/w growth[0] 0 bit 9 r/w sfberen 0 bit 8 r/w sdberen 0 bit 7 r/w stimen 0 bit 6 r/w stiuen 0 bit 5 r/w apsbfen 0 bit 4 r/w lrdien 0 bit 3 r/w laisen 0 bit 2 r/w losen 0 bit 1 r/w lofen 0 bit 0 r/w oofen 0 oofen, lofen, losen, laisen, lrdien, apsbfen, stiuen, stimen, sdberen, sfberen, growthen[1:0]: the above enable bits allows for the auto assertion of transmit lais based on the following conditions: - out of frame defect - loss of frame defect - loss of signal defect - line alarm indication signal defect - line remote defect indication defect - aps byte failure defect - section trace identifier unstable defect - section trace identifier mismatch defect - signal degrade ber defect - signal failure ber defect - growth defect when the bit is set high, the corresponding defect indication is ored with other defect indications and the result forces transmit lais. under transmit lais, an all ones pattern is written into the transmit line overhead and spe bytes. when the bit is set low, the corresponding defect indication does not affect the assertion of transmit lais.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 297 register 0728h: sarc path configuration bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 unused bit 10 unused bit 9 unused bit 8 unused bit 7 r/w prdien 0 bit 6 r/w perdi22 0 bit 5 r/w reserved 0 bit 4 r/w ploptrend 0 bit 3 r/w paisptrcfg[1] 0 bit 2 r/w paisptrcfg[0] 0 bit 1 r/w ploptrcfg[1] 0 bit 0 r/w ploptrcfg[0] 0 ploptrcfg[1:0]: the path loss of pointer configuration (ploptrcfg[1:0]) bits define the lop-p defect. when ploptrcfg[1:0] is set to 00b, an lop-p defect is declared when the pointer is in the lop state and an lop-p defect is removed when the pointer is not in the lop state. when ploptrcfg[1:0] is set to 01b, an lop-p defect is declared when the pointer or any of the concatenated pointers is in the lop state and an lop-p defect is removed when the pointer and all the concatenation pointers are not in the lop state. when ploptrcfg[1:0] is set to 10b, an lop-p defect is declared when the pointer or any of the concatenated pointers is in the lop state or in the ais state and an lop-p defect is removed when the pointer and all the concatenation pointers are not in the lop state or in the ais state. paisptrcfg[1:0]: the path ais pointer configuration (paisptrcfg[1:0]) bits define the ais-p defect. when paisptrcfg[1:0] is set to 00b, an ais-p defect is declared when the pointer is in the ais state and an ais-p defect is removed when the pointer is not in the ais state. when paisptrcfg[1:0] is set to 01b, an ais-p defect is declared when the pointer or any of the concatenated pointers is in the ais state and an ais-p defect is removed when the pointer and all the concatenation pointers are not in the ais state. when paisptrcfg[1:0] is set to 10b, an ais-p defect is declared when the pointer and all the concatenated pointers are in the ais state and an ais-p defect is removed when the pointer or any of the concatenation pointers is not in the ais state.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 298 ploptrend: the path loss of pointer removal (ploptrend) bit controls the removal of a lop-p defect when an ais-p defect is declared. when ploptrend is set to logic 1, a lop-p defect is terminated when an ais-p defect is declared. when ploptrend is set to logic 0, a lop-p defect is not terminated when an ais-p defect is declared. perdi22: the path enhance remote defect indication (perdi22) bit selects the path erdi persistence. when perdi22 is set to logic 1, a new path erdi indication is transmitted by the thpp for at least 22 frames. when perdi22 is set to logic 0, a new path erdi indication is transmitted transmitted by the thpp for at least 12 frames. prdien: the path remote defect indication enable (prdien) bit selects between the 1 bit rdi code and the 3 bits erdi code. when prdien is set to logic 1, the 1 bit rdi code is transmitted transmitted by the thpp. when prdien is set to logic 0, the 3 bit erdi code is transmitted transmitted by the thpp.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 299 register 0729h: sarc path ralm enable bit type function default bit 15 unused bit 14 unused bit 13 r/w pgrowth[1] 0 bit 12 r/w pgrowth[0] 0 bit 11 r/w ptimen 0 bit 10 r/w ptiuen 0 bit 9 r/w perdien 0 bit 8 r/w prdien 0 bit 7 r/w ppdien 0 bit 6 r/w puneqen 0 bit 5 r/w pplmen 0 bit 4 r/w ppluen 0 bit 3 r/w paisptren 0 bit 2 r/w ploptren 0 bit 1 r/w reserved 0 bit 0 r/w rsalmen 0 salmen, ploptren, paisptren, ppluen, pplmen, puneqen, ppdien, prdien, perdien, ptiuen, ptimen, pgrowthen[1:0]: the above enable bits allows for the generation of the ralm output based on the following conditions: - section alarm (register 06a3h) - path loss of pointer defect - path ais pointer defect - path payload label unstable defect - path payload label mismatch defect - path unequipped defect - path payload defect indication defect - path remote defect indication defect - path enhanced remote defect indication defect - path trace identifier unstable defect - path trace identifier mismatch defect - path growth defect when the bit is set high, the corresponding defect indication is ored with other defect indications to generate ralm. when the bit is set low, the corresponding defect indication does not affect ralm.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 300 register 072a: sarc path rpaisins enable bit type function default bit 15 unused bit 14 unused bit 13 r/w pgrowth[1] 0 bit 12 r/w pgrowth[0] 0 bit 11 r/w ptimen 0 bit 10 r/w ptiuen 0 bit 9 r/w perdien 0 bit 8 r/w prdien 0 bit 7 r/w ppdien 0 bit 6 r/w puneqen 0 bit 5 r/w pplmen 0 bit 4 r/w ppluen 0 bit 3 r/w paisptren 0 bit 2 r/w ploptren 0 bit 1 r/w reserved 0 bit 0 r/w rlaisinsen 0 rlaisinsen, ploptren, paisptren, ppluen, pplmen, puneqen, ppdien, prdien, perdien, ptiuen, ptimen, pgrowthen[1:0]: the above enable bits allows for the generation of receive path ais (ais-p) based on the following conditions: - receive lais (register 06a4h) - path loss of pointer defect - path ais pointer defect - path payload label unstable defect - path payload label mismatch defect - path unequipped defect - path payload defect indication defect - path remote defect indication defect - path enhanced remote defect indication defect - path trace identifier unstable defect - path trace identifier mismatch defect - path growth defect when the bit is set high, the corresponding defect indication is ored with other defect indications to generate receive ais-p. when under receive ais-p, a all ones pattern is inserted into the receive spe bytes. when the bit is set low, the corresponding defect indication does not affect the assertion of ais-p.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 301 register 0730h: sarc lop pointer status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r reserved x bit 10 r reserved x bit 9 r reserved x bit 8 r reserved x bit 7 r reserved x bit 6 r reserved x bit 5 r reserved x bit 4 r reserved x bit 3 r reserved x bit 2 r reserved x bit 1 r reserved x bit 0 r ploptrv x ploptrv: the path loss of pointer status (ploptrv) bit indicates the current status of the lop-p defect for sts-1/stm-0. when ploptrcfg register bits are set to 00b, ploptrv is asserted when the pointer is in the lop state and ploptrv is negated when the pointer is not in the lop state. when ploptrcfg register bits are set to 01b, ploptrv is asserted when the pointer or any of the concatenated pointers is in the lop state and ploptrv is negated when the pointer and all the concatenation pointers are not in the lop state. when ploptrcfg register bits are set to 10b, ploptrv is asserted when the pointer or any of the concatenated pointers is in the lop state or in the ais state and ploptrv is negated when the pointer and all the concatenation pointers are not in the lop state or in the ais state. when the ploptrend register bit is set to one, plopptrv is negated when a ais-p defect is detected.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 302 register 0731h: sarc lop pointer interrupt enable bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r/w reserved 0 bit 10 r/w reserved 0 bit 9 r/w reserved 0 bit 8 r/w reserved 0 bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w ploptre[1] 0 ploptre: the path loss of pointer interrupt enable (ploptre) bit controls the activation of the interrupt (intb) output. when this bit is set to logic 1, the pending interrupt will assert the interrupt (intb) output. when this bit is set to logic 0, the pending interrupt will not assert the interrupt (intb) output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 303 register 0732h: sarc lop pointer interrupt status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r reserved x bit 10 r reserved x bit 9 r reserved x bit 8 r reserved x bit 7 r reserved x bit 6 r reserved x bit 5 r reserved x bit 4 r reserved x bit 3 r reserved x bit 2 r reserved x bit 1 r reserved x bit 0 r ploptri[1] x ploptri: the path loss of pointer interrupt status (ploptri) bit is an event indicator for the sts- 1/stm-0 path #1. ploptri is set to logic 1 to indicate any changes in the status of ploptrv. this interrupt status bit is independent of the interrupt enable bit. ploptri is cleared to logic 0 when this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 304 register 0733h: sarc ais pointer status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r reserved x bit 10 r reserved x bit 9 r reserved x bit 8 r reserved x bit 7 r reserved x bit 6 r reserved x bit 5 r reserved x bit 4 r reserved x bit 3 r reserved x bit 2 r reserved x bit 1 r reserved x bit 0 r paisptrv[1] x paisptrv: the path ais pointer status (paisptrv) bit indicates the current status of the ais-p defect for sts-1/stm-0 #1. when paisptrcfg register bits are set to 00b, paisptrv is asserted when the pointer is in the ais state and paisptrv is negated when the pointer is not in the ais state. when paisptrcfg register bits are set to 01b, paisptrv is asserted when the pointer or any of the concatenated pointers is in the ais state and paisptrv is negated when the pointer and all the concatenation pointers are not in the ais state. when paisptrcfg register bits are set to 10b, paisptrv is asserted when the pointer and all the concatenated pointers are in the ais state and paisptrv is negated when the pointer or any of the concatenation pointers are not in the ais state.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 305 register 0734h: sarc ais pointer interrupt enable bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r/w reserved 0 bit 10 r/w reserved 0 bit 9 r/w reserved 0 bit 8 r/w reserved 0 bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w paisptre 0 paisptre: the path ais signal pointer interrupt enable (paisptre) bit controls the activation of of the interrupt (intb) output. when this bit is set to logic 1, the pending interrupt will assert the interrupt (intb) output. when this bit is set to logic 0, the pending interrupt will not assert the interrupt (intb) output.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 306 register 0735h: sarc ais pointer interrupt status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r reserved x bit 10 r reserved x bit 9 r reserved x bit 8 r reserved x bit 7 r reserved x bit 6 r reserved x bit 5 r reserved x bit 4 r reserved x bit 3 r reserved x bit 2 r reserved x bit 1 r reserved x bit 0 r paisptri x paisptri: the path ais pointer interrupt status (paisptri) bit is an event indicators for sts-1/stm-0 paths #1. paisptri is set to logic 1 to indicate any changes in the status of paisptrv. these interrupt status bits are independent of the interrupt enable bits. paisptri is cleared to logic 0 when this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 307 register 0740h: rcfp configuration bit type function default bit 15 r/w reserved 0 bit 14 r/w reserved 0 bit 13 r/w reserved 0 bit 12 r/w reserved 0 bit 11 r/w reserved 0 bit 10 r/w pos_sel 0 bit 9 r/w invert 0 bit 8 r/w strip_sel 0 bit 7 r/w reserved 0 bit 6 r/w idlepass 0 bit 5 r/w crcpass 0 bit 4 r/w crc_sel[1] 1 bit 3 r/w crc_sel[0] 1 bit 2 r/w rxotyp 0 bit 1 r/w descrmbl 1 bit 0 r/w prov 0 prov: the processor provision bit (prov) is used to enable the rcfp. when prov is logic 0, the rcfp atm and packet processors are disabled and will not transfer any valid data to the receive fifo interface. when prov is logic 1, the rcfp atm or packet processor is enabled and will process data presented to it and transfer data to the receive fifo (rxsdq). descrmbl: the descrmbl bit controls the descrambling of the packet or atm cell payload with the polynomial x 43 + 1. when descrmbl is set to logic 0, frame or cell payload descrambling is disabled. when descrmbl is set to logic 1, payload descrambling is enabled. rxotyp: the rxotyp bit determines if an incoming alarm signal (from ipais[x]) will stop a packet by simply asserting eop, (rxotyp set to logic 0), or by asserting both eop and err, (rxotyp set to logic 1). when rxotyp is set to logic 0, premature termination of the packet will result in that packet failing a fcs check. this bit is only valid when in pos mode. in atm mode the rcfp will finish processing any cell in progress and then stop until the alarm signal is cleared.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 308 crc_sel[1:0]: the crc select (crc_sel[1:0]) bits allow the control of the crc calculation according to the table below. for atm cells, the crc is calculated over the first four atm header bytes. for packet applications, the crc is calculated over the whole packet data, after byte destuffing and descrambling. table 9: functionality of the crc_sel[1:0] register bits crc_sel[1:0] hcs operation fcs operation 00 reserved no fcs verification 01 reserved reserved 10 crc-8 without coset polynomial crc-ccitt (2 bytes) 11 crc-8 with coset polynomial added crc-32 (4 bytes) crcpass: the crcpass bit controls the dropping of cells and packets based on the detection of a crc error. when in atm mode and when crcpass is a logic 0, cells containing an uncorrectable hcs error are dropped and the hcs verification state machine transitions to the 'detection mode'. cells containing a correctable hcs error have the error fixed (if hcs error correction is enabled), and the state machine transitions to the 'detection mode'. when crcpass is logic 1, cells are passed to the external fifo interface regardless of errors detected in the hcs. additionally, the hcs verification finite state machine will never lose cell delineation. regardless of the programming of this bit, atm cells are always dropped while the cell delineation state machine is in the 'hunt' or 'presync' states unless the delindis bit in this register is set to logic 1. when in pos mode and crcpass is logic 1, then packets with fcs errors are not marked as such and are passed to the external fifo interface as if no fcs error occurred. when crcpass is logic 0, then packets with fcs errors are marked with err. idlepass: the idlepass bit controls the function of the atm idle cell filter. it is only valid when in atm mode. when idlepass is written with logic 0, all cells that match the idle cell header pattern and idle cell header mask are filtered out. when idlepass is enabled, the idle cell header pattern and mask register bits are ignored. the default state of this bit and the bits in the rcfp idle cell header and mask register enable the dropping of idle cells.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 309 strip_sel: the frame check sequence stripping bit (strip_sel) selects the crc stripping mode of the rcfp. when strip_sel is logic 1, crc stripping is enabled. when strip_sel is logic 0, crc stripping is disabled. note that crc_sel[1:0] must not equal "00", (no crc) for stripping to be enabled. when stripping is enabled the received packet fcs or atm cell hcs byte(s) are not passed to the rxsdq fifo. when strip is disabled the received packet fcs are transferred over the fifo interface. when delindis is enabled, packets and cells are not delineated therefore the value of strip_sel is ignored. the strip_sel bit must be set to logic 1 if working in atm mode. invert: the data inversion bit (invert) configures the processor to logically invert the incoming stream before processing it. when invert is set to logic 1, the stream is logically inverted before processing. when invert is set to logic 0, the stream is not inverted before processing. pos_sel: the packet over sonet (pos_sel) bit selects the data type mode of the rcfp. when pos_sel is logic 1, pos mode is selected. when pos_sel is logic 0, atm mode is selected. reserved: all reserved bits must be set to their default values for proper operation.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 310 register 0741h: rcfp interrupt enable bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 r oofv x bit 8 r lofv x bit 7 r/w minle 0 bit 6 r/w maxle 0 bit 5 r/w abrte 0 bit 4 r/w xfere 0 bit 3 r/w ccrce 0 bit 2 r/w ucrce 0 bit 1 r/w oofe 0 bit 0 r/w lofe 0 lofe: the lofe bit enables the generation of an interrupt due to a change in the atm lcd state. when lofe is set to logic 1, the interrupt is enabled. oofe: the oofe bit enables the generation of an interrupt due to a change in atm cell delineation state or packet idle state. when oofe is set to logic 1, the interrupt is enabled. ucrce the ucrce bit enables the generation of an interrupt due to the detection of an uncorrectable atm hcs or packet fcs error. when ucrce is set to logic 1, the interrupt is enabled. reserved: the reserved bit should be set to logic 0 for proper operation. xfere: the xfere bit enables the generation of an interrupt when an accumulation interval is completed and new values are stored in the rcfp performance monitor counter holding registers. when xfere is set to logic 1, the interrupt is enabled.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 311 abrte: the abort packet enable bit enables the generation of an interrupt due to the reception of an aborted packet. when abrte is set to logic 1, the interrupt is enabled. maxle: the maximum length packet enable bit enables the generation of an interrupt due to the reception of a packet exceeding the programmable maximum packet length. when maxle is set to logic 1, the interrupt is enabled. minle: the minimum length packet enable bit enables the generation of an interrupt due to the reception of a packet that is smaller than the programmable minimum packet length. when minle is set to logic 1, the interrupt is enabled. lofv: the lofv bit gives the atm loss of cell delineation state. when lofv is logic 1, an out of cell delineation (lof) defect has persisted for the number of cells specified in the lcd count threshold register. when lofv is logic 0, the rcfp has been in cell delineation for the number of cells specified in the rcfp lcd count threshold register. the cell time period can be varied by using the lcdc[10:0] register bits in the rcfp lcd count threshold register. oofv: the oofv bit indicates the atm cell delineation or packet out of frame alignment state. when oofv is logic 1, the cell delineation state machine is in the 'hunt' or 'presync' states and is hunting for the cell boundaries or the packet processor is in idle state. when oofv is logic 0, the cell delineation state machine is in the 'sync' state (either correction or detection mode) and cells are passed through the receive fifo or the packet processor is not in idle state.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 312 register 0742h: rcfp interrupt indication and status bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 r minli x bit 6 r maxli x bit 5 r abrti x bit 4 r xferi x bit 3 r reserved x bit 2 r ucrci x bit 1 r oofi x bit 0 r lofi x lofi: the lofi bit is set to logic 1 when there is a change in the loss of cell delineation (lcd) state. the current value of the lcd state is available through the lof bit in this register. this bit is set to logic 0 immediately after a read to this register. this interrupt can be masked using lofe. oofi: the oofi bit is set to logic 1 when the rcfp atm cell processor enters or exits the sync state or the packet processor enters or exits the frame alignment state. the oofi bit is set to logic 0 immediately after a read to this register. this interrupt can be masked using oofe. ucrci: the ucrci bit is set to logic 1 when an uncorrectable atm hcs or packet fcs error is detected. this bit is set to logic 0 immediately after a read to this register. this interrupt can be masked using ucrce. reserved: this bit is not used.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 313 xferi: the xferi bit indicates that a transfer of accumulated counter data has occurred. logic 1 in this bit position indicates that the rcfp performance monitor counter holding registers have been updated. this update is initiated by writing to one of the counter register locations, or by writing to address 0000h. xferi is set to logic 0 after this register is read. this interrupt can be masked using xfere. abrti: the abrti bit indicates the generation of an interrupt due to the reception of an aborted packet. this interrupt can be masked using abrte. abrti is set to logic 0 after this register is read. maxli: the maxli bit indicates an interrupt due to the reception of a packet exceeding the programmable maximum packet length. this interrupt can be masked using maxle. maxli is set to logic 0 after this register is read. minli: the minli bit indicates an interrupt due to the reception of a packet that is smaller than the programmable minimum packet length. this interrupt can be masked using minle. minli is set to logic 0 after this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 314 register 0743h: rcfp minimum packet length bit type function default bit 15 r/w minpl[7] 0 bit 14 r/w minpl[6] 0 bit 13 r/w minpl[5] 0 bit 12 r/w minpl[4] 0 bit 11 r/w minpl[3] 0 bit 10 r/w minpl[2] 1 bit 9 r/w minpl[1] 0 bit 8 r/w minpl[0] 0 bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w rby_mode 0 bit 2 r/w reserved 0 bit 1 r/w reserved 1 bit 0 r/w reserved 0 reserved: the reserved bits should be set to their default values for proper operation.rby_mode: the receive byte counter mode (rby_mode) bit is used to select the mode in which the rby_ic[39:0] counters work. when rby_mode is logic 0, rby_ic[39:0] will count all bytes in received packets (including fcs and abort bytes) after the byte destuffing operation. when rby_mode is logic 1, rby_ic[39:0] will count all bytes in received packets (including fcs, abort, and stuff bytes) before the byte destuffing operation. flag bytes will not be counted in either case. the rby_mode bit is only valid when working in pos mode. minpl[7:0]: the minimum packet length (minpl[7:0]) bits are used to set the minimum packet length. packets smaller than this length are marked with an error. the packet length used here is defined as the number of bytes encapsulated into the pos frame after destuffing but including the fcs. the default minimum packet length is 4 octets. values smaller than 4 should not be used.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 315 register 0744h: rcfp maximum packet length bit type function default bit 15 r/w maxpl[16] 0 bit 14 r/w maxpl[15] 0 bit 13 r/w maxpl[14] 0 bit 12 r/w maxpl[13] 0 bit 11 r/w maxpl[12] 0 bit 10 r/w maxpl[11] 0 bit 9 r/w maxpl[10] 1 bit 8 r/w maxpl[9] 1 bit 7 r/w maxpl[8] 0 bit 6 r/w maxpl[7] 0 bit 5 r/w maxpl[6] 0 bit 4 r/w maxpl[5] 0 bit 3 r/w maxpl[4] 0 bit 2 r/w maxpl[3] 0 bit 1 r/w maxpl[2] 0 bit 0 r/w maxpl[1] 0 maxpl[16:1]: the maximum packet length (maxpl[16:0]) bits are used to set the maximum packet length. maxpl[0] is automatically set to logic 0. packets larger than this length are marked with an error. this maximum packet length defaults to 1.5 kbytes. the packet length used here is defined as the number of bytes encapsulated into the pos frame excluding byte stuffing but including the fcs. the default maximum packet length is 1536 octets. the maximum packet length allowed is 128 kbytes.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 316 register 0745h: rcfp lcd count threshold bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 r/w lcdc[10] 0 bit 9 r/w lcdc[9] 0 bit 8 r/w lcdc[8] 1 bit 7 r/w lcdc[7] 0 bit 6 r/w lcdc[6] 1 bit 5 r/w lcdc[5] 1 bit 4 r/w lcdc[4] 0 bit 3 r/w lcdc[3] 1 bit 2 r/w lcdc[2] 0 bit 1 r/w lcdc[1] 0 bit 0 r/w lcdc[0] 0 lcdc[10:0]: the lcdc[10:0] bits represent the number of consecutive cell periods the receive cell processor must be out of cell delineation before loss of cell delineation (lcd) is declared. likewise, lcd is not deasserted until the receive cell processor is in cell delineation for the number of cell periods specified by lcdc[10:0]. the default value of lcd[10:0] is 360, which translates to the following: table 10: average sts-x cell period versus lcd integration period format average cell period default lcd integration period sts-48c 176.9 ns 63.8 s sts-12c 707.5 ns 254.7 s
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 317 register 0746h: rcfp idle cell header and mask bit type function default bit 15 r/w gfc[3] 0 bit 14 r/w gfc[2] 0 bit 13 r/w gfc[1] 0 bit 12 r/w gfc[0] 0 bit 11 r/w pti[3] 0 bit 10 r/w pti[2] 0 bit 9 r/w pti[1] 0 bit 8 r/w clp 1 bit 7 r/w mgfc[3] 1 bit 6 r/w mgfc[2] 1 bit 5 r/w mgfc[1] 1 bit 4 r/w mgfc[0] 1 bit 3 r/w mpti[3] 1 bit 2 r/w mpti[2] 1 bit 1 r/w mpti[1] 1 bit 0 r/w mclp 1 mclp: the clp bit contains the mask pattern for the eighth bit of the fourth octet of the 53-octet cell. this mask is applied to this register to select the bits included in the cell filter. logic 1 in this bit position enables the clp bit in the pattern register to be compared. logic 0 causes the masking of the clp bit. the default enables the register bit comparison. mpti[3:0]: the mpti[3:0] bits contain the mask pattern for the fifth, sixth, and seventh bits of the fourth octet of the 53-octet cell. this mask is applied to the idle cell header field to select the bits included in the cell filter. a logic 1 in any bit position enables the corresponding bit in the pattern register to be compared. a logic 0 causes the masking of the corresponding bit. the default enables the register bit comparison. mgfc[3:0]: the mgfc[3:0] bits contain the mask pattern for the first, second, third, and fourth bits of the first octet of the 53-octet cell. this mask is applied to the idle cell header field to select the bits included in the cell filter. logic 1 in any bit position enables the corresponding bit in the pattern register to be compared. logic 0 causes the masking of the corresponding bit. the default enables the register bit comparison.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 318 clp: the clp bit contains the pattern to match in the eighth bit of the fourth octet of the 53-octet cell, in conjunction with the idle cell header and mask register bit. the idlepass bit in the rcfp configuration register must be set to logic 0 to enable dropping of cells matching this pattern. pti[2:0]: the pti[2:0] bits contain the pattern to match in the fifth, sixth, and seventh bits of the fourth octet of the 53-octet cell, in conjunction with the idle cell header and mask register bits. the idlepass bit in the rcfp configuration register must be set to logic 0 to enable dropping of cells matching this pattern. gfc[3:0]: the gfc[3:0] bits contain the pattern to match in the first, second, third, and fourth bits of the first octet of the 53-octet cell, in conjunction with the idle cell header and mask register bits. the idlepass bit in the rcfp configuration register must be set to logic 0 to enable dropping of cells matching this pattern. note that an all-zeros pattern must be present in the vpi and vci fields of the idle cell.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 319 register 0747h: rcfp receive byte/idle cell counter (lsb) bit type function default bit 15 to bit 0 r rby_ic[15:0] xxxx register 0748h: rcfp receive byte/idle cell counter bit type function default bit 15 to bit 0 r rby_ic[31:16] xxxx register 0749h: rcfp receive byte/idle cell counter (msb) bit type function default bit 15 to bit 8 r unused xxxx bit 7 to bit 0 r rby_ic[39:32] xxxx rby_ic[39:0]: when pos mode is selected, the rby_ic[39:0] bits indicate the number of bytes received within pos frames during the last accumulation interval. the byte counts include all user payload bytes, fcs bytes, and abort bytes. inclusion of stuffed bytes in the count is controlled by the rby_mode register bit. hdlc flags are not counted. when atm mode is selected, the rby_ic[39:0] bits indicate the number of idle cells received and passed to the fifo interface in the last accumulation interval. a write to any one of the rcfp performance monitor counter registers loads the registers with the current counter value and resets the internal 40 bit counter to 1 or 0. the counter reset value is dependent on if there was a count event during the transfer of the count to rcfp performance monitor counter registers. the counter should be polled regularly to avoid saturating. to allow for synchronization update with all other blocks, register 0000h can be written to initiate a global performance counter update.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 320 register 074ah: rcfp packet/cell counter (lsb) bit type function default bit 15 to bit 0 r rp_rc[15:0] xxxx register 074bh: rcfp receive packet/atm cell counter (msb) bit type function default bit 15 to bit 0 r rp_rc[31:16] xxxx rp_rc[31:0]: when pos mode is selected, the rp_rc[31:0] bits indicate the number of received good packets passed to the fifo interface during the last accumulation interval. when atm mode is selected, the rp_rc[31:0] bits indicate the number of received atm cells and passed to the fifo interface in the last accumulation interval. a write to any one of the rcfp performance monitor counter registers loads the registers with the current counter value and resets the internal 32 bit counter to 1 or 0. the counter reset value is dependent on if there was a count event during the transfer of the count to the rcfp performance monitor counter registers. the counter should be polled regularly to avoid saturating. to allow for synchronization update with all other blocks, register 0000h can be written to initiate a global performance counter update.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 321 register 074ch: rcfp receive erred fcs/hcs counter bit type function default bit 15 r efcs[15] x bit 14 r efcs[14] x bit 13 r efcs[13] x bit 12 r efcs[12] x bit 11 r efcs[11] x bit 10 r efcs[10] x bit 9 r efcs[9] x bit 8 r efcs[8] x bit 7 r efcs[7]/uhcs[7] x bit 6 r efcs[6]/uhcs[6] x bit 5 r efcs[5]/uhcs[5] x bit 4 r efcs[4]/uhcs[4] x bit 3 r efcs[3]/uhcs[3] x bit 2 r efcs[2]/uhcs[2] x bit 1 r efcs[1]/uhcs[1] x bit 0 r efcs[0]/uhcs[0] x efcs[15:0]: when pos mode is selected, the efcs[15:0] bits indicate the number of received fcs errors during the last accumulation interval. uhcs[7:0]: when atm mode is selected, the uhcs[7:0] bits indicate the number of uncorrectable hcs errors received in the last accumulation interval.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 322 register 074dh: rcfp receive aborted packet counter bit type function default bit 15 r rabr[15] x bit 14 r rabr[14] x bit 13 r rabr[13] x bit 12 r rabr[12] x bit 11 r rabr[11] x bit 10 r rabr[10] x bit 9 r rabr[9] x bit 8 r rabr[8] x bit 7 r rabr[7] x bit 6 r rabr[6] x bit 5 r rabr[5] x bit 4 r rabr[4] x bit 3 r rabr[3] x bit 2 r rabr[2] x bit 1 r rabr[1] x bit 0 r rabr[0] x rabr[15:0]: when pos mode is selected, the rabr[15:0] bits indicate the number of aborted packets received during the last accumulation interval. this counter is held at value 0 when atm mode is selected. a write to any one of the rcfp performance monitor registers loads the registers with the current counter value and resets the internal counter to 1 or 0. the counter reset value is dependent on if there was a count event during the transfer of the count to the receive aborted packet counter registers. the counter should be polled regularly to avoid saturating. to allow for synchronization update with all other blocks, register 0000h can be written to initiate a global performance counter update. .
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 323 register 074eh: rcfp receive minimum length packet error counter bit type function default bit 15 r rminl[15] x bit 14 r rminl[14] x bit 13 r rminl[13] x bit 12 r rminl[12] x bit 11 r rminl[11] x bit 10 r rminl[10] x bit 9 r rminl[9] x bit 8 r rminl[8] x bit 7 r rminl[7] x bit 6 r rminl[6] x bit 5 r rminl[5] x bit 4 r rminl[4] x bit 3 r rminl[3] x bit 2 r rminl[2] x bit 1 r rminl[1] x bit 0 r rminl[0] x rminl[15:0]: when pos mode is selected, the rminl[15:0] bits indicate the number of minimum length packet errors received during the last accumulation interval. this counter is held at value 0 when atm mode is selected. a write to any one of the rcfp performance monitor registers loads the registers with the current counter value and resets the internal counter to 1 or 0. the counter reset value is dependent on if there was a count event during the transfer of the count to the receive minimum length packet counter registers. the counter should be polled regularly to avoid saturating. to allow for synchronization update with all other blocks, register 0000h can be written to initiate a global performance counter update.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 324 register 074fh: rcfp receive maximum length packet error counter bit type function default bit 15 r rmaxl[15] x bit 14 r rmaxl[14] x bit 13 r rmaxl[13] x bit 12 r rmaxl[12] x bit 11 r rmaxl[11] x bit 10 r rmaxl[10] x bit 9 r rmaxl[9] x bit 8 r rmaxl[8] x bit 7 r rmaxl[7] x bit 6 r rmaxl[6] x bit 5 r rmaxl[5] x bit 4 r rmaxl[4] x bit 3 r rmaxl[3] x bit 2 r rmaxl[2] x bit 1 r rmaxl[1] x bit 0 r rmaxl[0] x rmaxl[15:0]: when pos mode is selected, the rmaxl[15:0] bits indicate the number of maximum length packet errors received during the last accumulation interval. this counter is held at value 0 when atm mode is selected. a write to any one of the rcfp performance monitor registers loads the registers with the current counter value and resets the internal counter to 1 or 0. the counter reset value is dependent on if there was a count event during the transfer of the count to the receive maximum length packet counter registers. the counter should be polled regularly to avoid saturating. to allow for synchronization update with all other blocks, register 0000h can be written to initiate a global performance counter update.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 325 register 0750h: tcfp configuration bit type function default bit 15 r/w fifo_erre 0 bit 14 r/w fifo_udre 0 bit 13 r/w xfere 0 bit 12 unused x bit 11 r/w reserved 0 bit 10 r/w reserved 0 bit 9 r/w reserved 0 bit 8 r/w pos_sel 0 bit 7 r/w crc_sel[1] 1 bit 6 r/w crc_sel[0] 1 bit 5 r/w flag[3] 0 bit 4 r/w flag[2] 0 bit 3 r/w flag[1] 0 bit 2 r/w flag[0] 0 bit 1 r/w scrmbl 1 bit 0 r/w prov 0 prov: the processor provision bit (prov) is used to enable the tcfp. when prov is logic 0, the tcfp atm and packet processors are disabled and will not request data from the txsdq fifo interface and will respond to data requests with all 1?s data. when prov is logic 1, the tcfp atm or packet processor is enabled and will respond to data requests with valid data after requesting and processing data from the txsdq fifo interface. scrmbl: the scrmbl bit controls the scrambling of the packet data stream or atm cell payload. when scrmbl is a logic 1, scrambling is enabled. when scrmbl is a logic 0, scrambling is disabled. flag[3:0]: the flag insertion control (flag[3:0]) configures the minimum number of flag bytes the packet processor inserts between packets. the minimum number of flags (01111110) inserted between packets is shown in the table below. flag[3:0] are used only in pos mode. table 11: selection of the number of flag bytes flag[3:0] minimum number of flag bytes
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 326 0000 1 flag 0001 2 flags 0010 4 flags 0011 8 flags 0100 16 flags 0101 32 flags 0110 64 flags 0111 128 flags 1000 256 flags 1001 512 flags 1010 1024 flags 1011 2048 flags 1100 4096 flags 1101 8192 flags 1110 16384 flags 1111 32768 flags crc_sel[1:0]: the crc select (crc_sel[1:0]) bits allow the control of the crc calculation according to the table below. for atm cells, the crc is calculated over the first four atm header bytes. for packet applications, the crc is calculated over the whole packet data, before byte stuffing and scrambling. table 12: crc mode selection crc_sel[1 :0] hcs operation fcs operation 00 reserved no fcs inserted 01 reserved no fcs inserted 10 crc-8 without coset polynomial crc-ccitt (2 bytes) 11 crc-8 with coset polynomial added crc-32 (4 bytes) pos_sel: the pos_sel bit enables the pos hdlc frame processing mode. when pos_sel is set to logic 1, pos processing will occur. when pos_sel is set to logic 0, atm mode is selected. reserved: the reserved bits should be set to logic 0 for proper operation.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 327 xfere: the xfere bit enables the generation of an interrupt when an accumulation interval is completed and new values are stored in the transmitted packet/cell counter, transmitted byte counter, and aborted packet counter holding registers. when xfere is set to logic 1, the interrupt is enabled. fifo_udre: the fifo_udre bit enables the generation of an interrupt due to a fifo underrun. when fifo_udre is set to logic 1, the interrupt is enabled the signal intb will be set to logic 0 whenever fifo_unri is set to logic 1. fifo_erre: the fifo_erre bit enables the generation of an interrupt due to a fifo error. when fifo_erre is set to logic 1, the interrupt is enabled and the signal intb will be set to logic 0 whenever fifo_erri is set to logic 1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 328 register 0751h: tcfp interrupt indication bit type function default bit 15 r fifo_erri 0 bit 14 r fifo_udri 0 bit 13 r xferi 0 bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 unused x xferi: the xferi bit indicates that a transfer of accumulated counter data has occurred. a logic 1 in this bit position indicates that the transmitted cell/packet counter, transmitted byte counter, and aborted packet counter holding registers have been updated. this update is initiated by writing to one of the tcfp counter register locations, or initiating a global performance monitor update by writing to register 0000h. xferi is set to logic 0 when this register is read. fifo_udri: the fifo_udri bit is set high when an attempt is made to read from the fifo while it is empty. this is considered a system error. this bit is set to logic 0 immediately after a read to this register. fifo_erri: this bit is set to one when an error is detected on the read side of the fifo. this error can be caused by an abnormal sequence of tsop and teop signals or the assertion of fifo_err. this can normally be caused by a previous fifo overrun or underrun condition or a user asserted error from the pos-phy l3 interface. this bit is reset immediately after a read to this register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 329 register 0752h: tcfp idle/unassigned atm cell header bit type function default bit 15 r/w gfc[3] 0 bit 14 r/w gfc[2] 0 bit 13 r/w gfc[1] 0 bit 12 r/w gfc[0] 0 bit 11 r/w pti[2] 0 bit 10 r/w pti[1] 0 bit 9 r/w pti[0] 0 bit 8 r/w clp 1 bit 7 r/w payld[7] 0 bit 6 r/w payld[6] 1 bit 5 r/w payld[5] 1 bit 4 r/w payld[4] 0 bit 3 r/w payld[3] 1 bit 2 r/w payld[2] 0 bit 1 r/w payld[1] 1 bit 0 r/w payld[0] 0 payld[7:0]: the payld[7:0] (idle cell payload) value reflects the payload bytes which will be inserted into the atm idle cell generated by the tcfp. clp: the clp (cell loss priority) bit contains the eighth bit position of the fourth octet of the idle/unassigned cell pattern. cell rate decoupling is accomplished by transmitting idle cells when the tcfp detects that no outstanding cells are available from the external fifo and data is requested on the tcfp egress interface. additionally, xoff can be used to force the transmission of idle/unassigned cells in atm mode. pti[2:0]: the pti[2:0] (payload type) bits contain the fifth, sixth, and seventh bit positions of the fourth octet of the idle/unassigned cell pattern. idle cells are transmitted when the tcfp detects that no outstanding cells are available from the external fifo and data is requested on the tcfp egress interface. additionally, xoff can be used to force the transmission of idle/unassigned cells in atm mode.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 330 gfc[3:0]: the gfc[3:0] (generic flow control) bits contain the first, second, third, and fourth bit positions of the first octet of the idle/unassigned cell pattern. idle/unassigned cells are transmitted when the tcfp detects that no outstanding cells are available from the fifo and data is requested on the tcfp egress interface. additionally, xoff can be used to force the transmission of idle/unassigned cells in atm mode. the all zeros pattern is transmitted in the vci and vpi fields of the idle/unassigned cell.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 331 register 0753h: tcfp diagnostics bit type function default bit 15 r/w dcrc[7] 0 bit 14 r/w dcrc[6] 0 bit 13 r/w dcrc[5] 0 bit 12 r/w dcrc[4] 0 bit 11 r/w dcrc[3] 0 bit 10 r/w dcrc[2] 0 bit 9 r/w dcrc[1] 0 bit 8 r/w dcrc[0] 0 bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w tx_byte_mode 0 bit 4 r/w xoff 0 bit 3 r/w invert 0 bit 2 r/w reserved 0 bit 1 r/w reserved 1 bit 0 r/w reserved 1 reserved: the reserved bits should be set to their default values for proper operation. invert: the data inversion bit (invert) configures the atm or packet processor to logically invert the outgoing data stream. when invert is set to logic 1, the outgoing data stream is logically inverted. the outgoing data stream is not inverted when invert is set to logic 0. xoff: the xoff serves as a transmission enable bit. when xoff is set to logic 0, atm cells or packets are transmitted normally. when xoff is set to logic 1, the cell or packet currently being transmitted is completed and then transmission is suspended. when xoff is set to logic 1, the tcfp will not request data from the fifo. atm idle cells or hdlc flags will be sent on the tcfp egress interface. tx_byte_mode: the transmit byte counter mode (tx_byte_mode) bit is used to select the mode in which the tx_byte[39:0] counters work. when tx_byte_mode is logic 0, tx_byte[39:0] will count all bytes in transmitted packets (including fcs and abort bytes) before the byte stuffing operation. when tx_byte_mode is logic 1, tx_byte[39:0] will count all bytes in
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 332 transmitted packets (including fcs, abort, and stuff bytes) after the byte stuffing operation. flag bytes will not be counted in either case. the tx_byte_mode bit is only valid when working in pos mode. dcrc[7:0]: the diagnostic crc word (dcrc[7:0]) configures the atm or packet processor to logically invert bits in the inserted crc on the outgoing data stream for diagnostic purposes. when any bit in dcrc[7:0] is set to logic 1, the corresponding bit in the fcs value inserted by the pos processor or the hcs value inserted by the atm processor is logically inverted. dcrc[7:0] is ignored when no fcs is inserted. each dcrc[x] bit will cause a bit error in each byte of the 2 byte or 4 byte fcs.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 333 register 0754h: tcfp transmit cell/packet counter (lsb) bit type function default bit 15 to bit 0 r tx_cell[15:0] xxxx register 0755h: tcfp transmit cell/packet counter (msb) bit type function default bit 15 to bit 0 r tx_cell[31:16] xxxx tx_cell[31:0]: the tx_cell[31:0] bits indicate the number of cells or non-aborted packets transmitted to the tcfp egress stream during the last accumulation interval. atm idle cells, hdlc flags, and hdlc abort bytes inserted into the transmission stream are not counted. a write to any one of the tcfp transmit cell/packet counter registers loads the registers with the current counter value and resets the internal 32 bit counter to 1 or 0. the counter reset value is dependent on if there was a count event during the transfer of the count to the transmit cell/packet counter registers. the counter should be polled regularly to avoid saturating. to allow for synchronization update with all other blocks, register 0000h can be written to initiate a global performance counter update.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 334 register 0756h: tcfp transmit byte counter (lsb) bit type function default bit 15 to bit 0 r tx_byte[15:0] xxxx register 0757h: tcfp transmit byte counter bit type function default bit 15 to bit 0 r tx_byte[31:16] xxxx register 0758h: tcfp transmit byte counter (msb) bit type function default bit 15 to bit 8 unused xx bit 7 to bit 0 r tx_byte[39:32] xx tx_byte[39:0]: the tx_ byte[39:0] bits indicate the number of bytes in packets transmitted to the tcfp egress stream during the last accumulation interval. the byte counts include all user payload bytes, fcs bytes, and abort bytes. inclusion of stuffed bytes is controlled by the tx_byte_mode register bit. hdlc flags are not counted. the tx_byte[39:0] counters are only valid when processing packets. a write to any one of the tcfp transmit byte counter registers loads the registers with the current counter value and resets the internal 40 bit counter to 1 or 0. the counter reset value is dependent on if there was a count event during the transfer of the count to the transmit byte counter registers. the counter should be polled regularly to avoid saturating. to allow for synchronization update with all other blocks, register 0000h can be written to initiate a global performance counter update.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 335 register 0759h: tcfp aborted packet counter bit type function default bit 15 r tx_abt[15] x bit 14 r tx_abt[14] x bit 13 r tx_abt[13] x bit 12 r tx_abt[12] x bit 11 r tx_abt[11] x bit 10 r tx_abt[10] x bit 9 r tx_abt[9] x bit 8 r tx_abt[8] x bit 7 r tx_abt[7] x bit 6 r tx_abt[6] x bit 5 r tx_abt[5] x bit 4 r tx_abt[4] x bit 3 r tx_abt[3] x bit 2 r tx_abt[2] x bit 1 r tx_abt[1] x bit 0 r tx_abt[0] x tx_abt[15:0]: the tx_ abt[15:0] bits indicate the number aborted packets transmitted to the tcfp egress stream during the last accumulation interval. these counters are only valid when processing packets. a write to any one of the tcfp transmit byte counter registers loads the registers with the current counter value and resets the internal 16 bit counter to 1 or 0. the counter reset value is dependent on if there was a count event during the transfer of the count to the transmit byte counter registers. the counter should be polled regularly to avoid saturating. to allow for synchronization update with all other blocks, register 0000h can be written to initiate a global performance counter update.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 336 register 0760h : rxsdq fifo reset bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r rxsdqtip x bit 0 r/w sdqrst 1 sdqrst: this bit is used to reset the rxsdq. the rxsdq comes up in reset. it should be taken out of reset by writing a 0 to this bit. the user can reset the sdq at any time by writing a 1 to this bit, and then writing a 0. reset flushes all the data in the fifos, resets the read and write pointers and resets all counters. the configuration information is not changed by reset. rxsdqtip: the rxsdqtip bit indicates that the rxsdq counters are in the process of being transferred to their holding registers. a transfer is initialized by writing to the s/uni-2488 identity, and global performance monitor update register (0000h).
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 337 register 0761h : rxsdq fifo interrupt enable bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w reserved 0 bit 2 r/w eope 0 bit 1 r/w sope 0 bit 0 r/w ofle 0 ofle: when this bit is set to 1, fifo overflows cause the intb output to be asserted. if this bit is set to 0, fifo overflows do not cause intb to be asserted. sope: when this bit is set to 1, bad sop signals cause the intb output to be asserted. if this bit is set to 0, bad sop signals do not cause intb to be asserted. eope: when this bit is set to 1, bad eop signals cause the intb output to be asserted. if this bit is set to 0, bad eop signals do not cause intb to be asserted. reserved: this bit should be set to logic 0 for proper operation.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 338 register 0763h : rxsdq fifo overflow port and interrupt indication bit type function default bit 15 unused x bit 14 unused x bit 13 r ofl_fifo[5] x bit 12 r ofl_fifo[4] x bit 11 r ofl_fifo[3] x bit 10 r ofl_fifo[2] x bit 9 r ofl_fifo[1] x bit 8 r ofl_fifo[0] x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r ofli x ofli: this bit is set when there is a fifo overflow condition. this bit is cleared when read by the user. ofl_fifo[5:0]: these bits are used to indicate the fifo identity. this field should contain the same number as the fifo_number [5:0] field in rxsdq fifo indirect configuration register; otherwise, an system error should be declared. these bits are valid only when the interrupt bit is logic 1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 339 register 0764h : rxsdq fifo sop error port and interrupt indication bit type function default bit 15 unused x bit 14 unused x bit 13 r sop_fifo[5] x bit 12 r sop_fifo[4] x bit 11 r sop_fifo[3] x bit 10 r sop_fifo[2] x bit 9 r sop_fifo[1] x bit 8 r sop_fifo[0] x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r sopi x sopi: this bit is set when two sops arrive consecutively on the fifo without being separated by a eop. this bit is cleared when read by the user. sop_fifo[5:0]: these bits are used to indicate the fifo identity. this field should contain the same number as the fifo_number [5:0] field in rxsdq fifo indirect configuration register; otherwise, an system error should be declared. these bits are valid only when the interrupt bit is logic 1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 340 register 0765h : rxsdq fifo eop error port and interrupt indication bit type function default bit 15 unused x bit 14 unused x bit 13 r eop_fifo[5] x bit 12 r eop_fifo[4] x bit 11 r eop_fifo[3] x bit 10 r eop_fifo[2] x bit 9 r eop_fifo[1] x bit 8 r eop_fifo[0] x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r eopi x eopi: this bit is set when two eops arrive consecutively on the fifo without being separated by a sop. this bit is cleared when read by the user. eop_fifo[5:0]: these bits are used to indicate the fifo identity. this field should contain the same number as the fifo_number [5:0] field in rxsdq fifo indirect configuration register; otherwise, an system error should be declared. these bits are valid only when the interrupt bit is logic 1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 341 register 0768h : rxsdq fifo indirect address bit type function default bit 15 r busy x bit 14 r/w rwb 0 bit 13 w flush 0 bit 12 r empty x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 r/w phyid[5] 0 bit 4 r/w phyid[4] 0 bit 3 r/w phyid[3] 0 bit 2 r/w phyid[2] 0 bit 1 r/w phyid[1] 0 bit 0 r/w phyid[0] 0 this is an indirect register that is used to specify the address of the fifo that the user is setting up or reading the setup for. a fifo needs to be configured according to a set of rules defined in the operations section. in order to change the current setup of a fifo, it is recommended that the user reads the existing setup information first, makes any modifications as required, and writes back the information. phyid[5:0]: this is a 6-bit number that is used to describe the current fifo being addressed by the rest of the fifo setup registers ? the rxsdq fifo indirect configuration, rxsdq fifo buffer available threshold, rxsdq fifo data available threshold and rxsdq fifo cells and packets count. this field should be set to all zeros. empty: this read-only bit indicates if the requested fifo is empty. when this bit is read as 1, the fifo number specified in phyid[5:0] in this register is empty. before reconfiguring a disabled fifo, this bit needs to be sampled at logic 1 indicating that the fifo is empty. flush: this is a write-only bit used to discard all the current data in a specified fifo. this should typically be used if a non-empty fifo needs to be reconfigured.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 342 rw b: this bit is used to indicate whether the user is writing the setup of a fifo, or reading all setup information of a fifo. this bit is used in conjunction with the busy bit. when this bit is set to 1, all the available setup information of the fifo requested in phyid[5:0] is available in the registers rxsdq fifo indirect configuration, rxsdq fifo indirect buffer available threshold, rxsdq fifo indirect data available threshold, and rxsdq fifo indirect cells and packets count. when this bit is set to 0, the user is writing the configuration of a fifo. busy: this is a read-only bit is used to indicate to the user that the information requested for the fifo specified in bits phyid[5:0] is in the process of being updated. if this bit is sampled to be 1, the update is still in progress. if this bit is sampled 0, the information for the fifo is now available in the accessed register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 343 register 0769h : rxsdq fifo indirect configuration bit type function default bit 15 r/w enable 0 bit 14 r/w pos_sel 0 bit 13 r/w fifo_number[5] 0 bit 12 r/w fifo_number[4] 0 bit 11 r/w fifo_number[3] 0 bit 10 r/w fifo_number[2] 0 bit 9 r/w fifo_number[1] 0 bit 8 r/w fifo_number[0] 0 bit 7 r/w fifo_bs[1] 0 bit 6 r/w fifo_bs[0] 1 bit 5 unused x bit 4 r/w block_ptr[4] 0 bit 3 r/w block_ptr[3] 0 bit 2 r/w block_ptr[2] 0 bit 1 r/w block_ptr[1] 0 bit 0 r/w block_ptr[0] 0 block_ptr[4:0]: this is a 5-bit number that is calculated and programmed by the user based on the number of phys, the size of each fifo, and total number of fifos required by the system. the rules governing this calculation are in the operations section. fifo_bs[1:0]: this 2-bit number denotes the size in blocks of fifo for the phyid specified in the rxsdq fifo indirect address register. the bandwidth is related to the size of the fifo that will be allocated to the phy. the values to be programmed are given in the operations section. fifo_number[5:0]: this is a 6-bit internal fifo number that is used to associate a given phy id with a fifo. this allows the user to flexibly use the sdq to map any fifo of any size to any phy id. the values to be programmed are given in the operations section. pos_sel: this bit is set to 1 if the fifo needs to be configured as a packet fifo. by default, the fifos are configured as atm cell fifos.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 344 enable: writing a 0 to this bit disables a fifo. if previously enabled, a disabled fifo does not accept any new data into it, but continues to assert data available internally until it is drained completely. in order to reconfigure fifos during operation, they need to be disabled first.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 345 register 076ah : rxsdq fifo indirect data available threshold bit type function default bit 15 r/w dt[7] 0 bit 14 r/w dt[6] 0 bit 13 r/w dt[5] 0 bit 12 r/w dt[4] 0 bit 11 r/w dt[3] 0 bit 10 r/w dt[2] 0 bit 9 r/w dt[1] 1 bit 8 r/w dt[0] 1 bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 1 bit 0 r/w reserved 1 this register is used to set the data available threshold for a fifo. this threshold is explained in the operations section. a fifo does not need to be enabled to set this threshold. in order to change this value for a fifo, the user should first disable it, write in the new value, and enable it again. reserved: the reserved bits should be set to their default values for proper operation. dt[7:0]: these bits specify the data available threshold for the fifo selected by the rxsdq fifo indirect address register?s phyid[5:0] bits. when this threshold is being set, these bits are written to by the user, and when this threshold is being read, these bits hold the previously configured data. the threshold is equal to dt[7:0] + 1. this threshold is set in 16 byte blocks. this threshold can never be greater than the size of the fifo. the absolute maximum value is dt[7:0] +1 = 16. this number should be a standard fraction of the fifo size in blocks. in the case of atm fifos, this number should be set to a value of dt[7:0] = 3 (atm cells are 4 blocks long).
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 346 register 076bh : rxsdq fifo indirect cells and packets count bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r count[3] x bit 2 r count[2] x bit 1 r count[1] x bit 0 r count[0] x count[3:0]: these read-only bits hold the last sampled count for the fifo requested for in the rxsdq fifo indirect address register?s phyid[5:0] bits. this register is latched when register 0000h is written to for a global performance monitor update. after the count is latched into the register, the internal counter is reset to 0, and starts counting again. when this counter reaches it?s maximum count, it rolls over. this register is for internal diagnostics only.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 347 register 076ch : rxsdq fifo cells and packets accepted aggregate count (lsb) bit type function default bit 15 to bit 0 r acount[15:0] x register 076dh : rxsdq fifo cells and packets accepted aggregate count (msb) bit type function default bit 15 to bit 0 r acount[31:16] x acount[31:0]: these bits display the aggregate count of all the pos packets and atm cells that are accepted by the rxsdq. this register is latched when register 0000h is written to for a global performance monitor update. after the count is latched into the register, the internal counter is reset to 0, and starts counting again. when this counter reaches it?s maximum count, it holds the value, and does not roll over.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 348 register 076eh: rxsdq fifo cells and packets dropped aggregate count bit type function default bit 15 r dcount[15] x bit 14 r dcount[14] x bit 13 r dcount[13] x bit 12 r dcount[12] x bit 11 r dcount[11] x bit 10 r dcount[10] x bit 9 r dcount[9] x bit 8 r dcount[8] x bit 7 r dcount[7] x bit 6 r dcount[6] x bit 5 r dcount[5] x bit 4 r dcount[4] x bit 3 r dcount[3] x bit 2 r dcount[2] x bit 1 r dcount[1] x bit 0 r dcount[0] x dcount[15:0]: these bits display the aggregate count of all the pos packets and atm cells that are dropped by the rxsdq due to fifo overflows. this register is latched when register 0000h is written to for a global performance monitor update. after the count is latched into the register, the internal counter is reset to 0, and starts counting again. when this counter reaches it?s maximum count, it holds the value, and does not roll over.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 349 register 0770h: txsdq fifo reset bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r txsdqtip x bit 0 r/w sdqrst 1 sdqrst: this bit is used to reset the txsdq. the txsdq comes up in reset. it should be taken out of reset by writing a 0 to this bit. the user can reset the sdq at any time by writing a 1 to this bit, and then writing a 0. reset flushes all the data in the fifos, resets the read and write pointers and resets all counters. the configuration information is not changed by reset. txsdqtip: the txsdqtip bit indicates that the txsdq counters are in the process of being transferred to their holding registers. a transfer is initialized by writing to the s/uni-2488 identity, and global performance monitor update register (0000h).
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 350 register 0771h: txsdq fifo interrupt enable bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w reserved 0 bit 2 r/w eope 0 bit 1 r/w sope 0 bit 0 r/w ofle 0 ofle: when this bit is set to 1, fifo overflows cause the intb output to be asserted. if this bit is set to 0, fifo overflows do not cause intb to be asserted. sope: when this bit is set to 1, bad sop signals cause the intb output to be asserted. if this bit is set to 0, bad sop signals do not cause intb to be asserted. eope: when this bit is set to 1, bad eop signals cause the intb output to be asserted. if this bit is set to 0, bad eop signals do not cause intb to be asserted. reserved: this bit should be set to logic 0 for proper operation.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 351 register 0773h: txsdq fifo overflow port and interrupt indication bit type function default bit 15 unused x bit 14 unused x bit 13 r ofl_fifo[5] x bit 12 r ofl_fifo[4] x bit 11 r ofl_fifo[3] x bit 10 r ofl_fifo[2] x bit 9 r ofl_fifo[1] x bit 8 r ofl_fifo[0] x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r ofli x ofli: this bit is set when there is a fifo overflow condition. this bit is cleared when read by the user. ofl_fifo[5:0]: these bits are used to indicate the fifo identity. this field should contain the same number as the fifo_number [5:0] field in txsdq fifo indirect configuration register; otherwise, an system error should be declared. these bits are valid only when the interrupt bit is logic 1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 352 register 0774h: txsdq fifo sop error port and interrupt indication bit type function default bit 15 unused x bit 14 unused x bit 13 r sop_fifo[5] x bit 12 r sop_fifo[4] x bit 11 r sop_fifo[3] x bit 10 r sop_fifo[2] x bit 9 r sop_fifo[1] x bit 8 r sop_fifo[0] x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r sopi x sopi: this bit is set when two sops arrive consecutively on the fifo without being separated by a eop. this bit is cleared when read by the user. sop_fifo[5:0]: these bits are used to indicate the fifo identity. this field should contain the same number as the fifo_number [5:0] field in txsdq fifo indirect configuration register; otherwise, an system error should be declared. these bits are valid only when the interrupt bit is logic 1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 353 register 0775h: txsdq fifo eop error port and interrupt indication bit type function default bit 15 unused x bit 14 unused x bit 13 r eop_fifo[5] x bit 12 r eop_fifo[4] x bit 11 r eop_fifo[3] x bit 10 r eop_fifo[2] x bit 9 r eop_fifo[1] x bit 8 r eop_fifo[0] x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r eopi x eopi: this bit is set when two eops arrive consecutively on the fifo without being separated by a sop. this bit is cleared when read by the user. eop_fifo[5:0]: these bits are used to indicate the fifo identity. this field should contain the same number as the fifo_number [5:0] field in txsdq fifo indirect configuration register; otherwise, an system error should be declared. these bits are valid only when the interrupt bit is logic 1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 354 register 0778h: txsdq fifo indirect address bit type function default bit 15 r busy x bit 14 r/w rwb 0 bit 13 w flush 0 bit 12 r empty x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 r/w phyid[5] 0 bit 4 r/w phyid[4] 0 bit 3 r/w phyid[3] 0 bit 2 r/w phyid[2] 0 bit 1 r/w phyid[1] 0 bit 0 r/w phyid[0] 0 this is an indirect register that is used to specify the address of the fifo that the user is setting up or reading the setup for. a fifo needs to be configured according to a set of rules defined in the operations section. in order to change the current setup of a fifo, it is recommended that the user reads the existing setup information first, makes any modifications as required, and writes back the information. phyid[5:0]: this is a 6-bit number that is used to describe the current fifo being addressed by the rest of the fifo setup registers ? the txsdq fifo indirect configuration, txsdq fifo buffer available threshold, txsdq fifo data available threshold and txsdq fifo cells and packets count. this field should be set to all zeros. empty: this read-only bit indicates if the requested fifo is empty. when this bit is rad as 1, the fifo number specified in phyid[5:0] in this register is empty. before reconfiguring a disabled fifo, this bit needs to be sampled at logic 1 indicating that the fifo is empty. flush: this is a write-only bit used to discard all the current data in a specified fifo. this should typically be used if a non-empty fifo needs to be reconfigured.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 355 rw b: this bit is used to indicate whether the user is writing the setup of a fifo, or reading all setup information of a fifo. this bit is used in conjunction with the busy bit. when this bit is set to 1, all the available setup information of the fifo requested in phyid[5:0] is available in the registers rxsdq fifo indirect configuration, rxsdq fifo indirect buffer available threshold, rxsdq fifo indirect data available threshold, and rxsdq fifo indirect cells and packets count. when this bit is set to 0, the user is writing the configuration of a fifo. busy: this is a read-only bit is used to indicate to the user that the information requested for the fifo specified in bits phyid[5:0] is in the process of being updated. if this bit is sampled to be 1, the update is still in progress. if this bit is sampled 0, the information for the fifo is now available in the accessed register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 356 register 0779h: txsdq fifo indirect configuration bit type function default bit 15 r/w enable 0 bit 14 r/w pos_sel 0 bit 13 r/w fifo_number[5] 0 bit 12 r/w fifo_number[4] 0 bit 11 r/w fifo_number[3] 0 bit 10 r/w fifo_number[2] 0 bit 9 r/w fifo_number[1] 0 bit 8 r/w fifo_number[0] 0 bit 7 r/w fifo_bs[1] 0 bit 6 r/w fifo_bs[0] 1 bit 5 unused x bit 4 r/w block_ptr[4] 0 bit 3 r/w block_ptr[3] 0 bit 2 r/w block_ptr[2] 0 bit 1 r/w block_ptr[1] 0 bit 0 r/w block_ptr[0] 0 block_ptr[4:0]: this is a 5-bit number that is calculated and programmed by the user based on the number of phys, the size of each fifo, and total number of fifos required by the system. the rules governing this calculation are in the operations section. fifo_bs[1:0]: this 2-bit number denotes the size in blocks of fifo for the phyid specified in the txsdq fifo indirect address register. the bandwidth is related to the size of the fifo that will be allocated to the phy. the values to be programmed are given in the operations section. fifo_number[5:0]: this is a 6-bit internal fifo number that is used to associate a given phy id with a fifo. this allows the user to flexibly use the sdq to map any fifo of any size to any phy id. the values to be programmed are given in the operations section. pos_sel: this bit is set to 1 if the fifo needs to be configured as a packet fifo. by default, the fifos are configured as atm cell fifos.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 357 enable: writing a 0 to this bit disables a fifo. if previously enabled, a disabled fifo does not accept any new data into it, but continues to assert data available internally until it is drained completely. in order to reconfigure fifos during operation, they need to be disabled first.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 358 register 077ah: txsdq fifo indirect data and buffer available thresholds bit type function default bit 15 r/w dt[7] 0 bit 14 r/w dt[6] 0 bit 13 r/w dt[5] 0 bit 12 r/w dt[4] 0 bit 11 r/w dt[3] 0 bit 10 r/w dt[2] 0 bit 9 r/w dt[1] 1 bit 8 r/w dt[0] 1 bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r/w bt[4] 0 bit 3 r/w bt[3] 0 bit 2 r/w bt[2] 0 bit 1 r/w bt[1] 1 bit 0 r/w bt[0] 1 this register is used to set the data and buffer available thresholds for a fifo. these thresholds are explained in the operations section. a fifo does not need to be enabled to set this threshold. in order to change a value for a fifo, the user should first disable it, write in the new value, and enable it again. bt[4:0]: these bits specify the buffer available threshold for the fifo specified in phyid[5:0] bits in the txsdq fifo indirect address register. when this threshold is being set, these bits are written to by the user, and when this threshold is being read, these bits hold the previously configured data. the threshold is equal to bt[4:0] + 1. this threshold is set in 16 byte blocks. this threshold can never be greater than the size of the fifo being configured, and the absolute maximum value is bt[4:0] +1 = 32. this number should be a standard fraction of the fifo size in blocks. in the case of atm fifos, this number should be et to a value of bt[4:0] = 3 since atm cells are 4 bytes in size. dt[7:0]: these bits specify the data available threshold for the fifo selected by the txsdq fifo indirect address register phyid[5:0] bits. when this threshold is being set, these bits are written to by the user, and when this threshold is being read, these bits hold the previously configured data. the threshold is equal to dt[7:0] + 1.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 359 this threshold is set in 16 byte blocks. this threshold can never be greater than the size of the fifo being configured, and the absolute maximum value is dt[7:0] +1 = 192. this number should be a standard fraction of the fifo size in blocks. in the case of atm fifos, this number should be set to a value of dt[7:0] = 3 (atm cells are 4 blocks long). the dt[7:0] threshold sets the level at which the cell/packet processors (tcfp) blocks can begin transmission of a cell or packet. once transmission of a cell or packet begins, it cannot be stopped so this threshold should be set to a value which guarantees that the utopia/pos- phy interface can write to the fifo in due time to prevent fifo underruns. for packet data, it is recommended that dt[7:0] be set to a larger value about equal to 1/2 or 2/3 the size of the fifo.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 360 register 077bh: txsdq fifo indirect cells and packets count bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r count[3] x bit 2 r count[2] x bit 1 r count[1] x bit 0 r count[0] x count[3:0]: these read-only bits hold the last sampled count for the fifo requested for in txsdq fifo indirect address register phyid[5:0] bits. this register is latched when register 0000h is written to for a global performance monitor update. after the count is latched into the register, the internal counter is reset to 0, and starts counting again. when this counter reaches it?s maximum count, it rolls over. this register is for internal diagnostics only.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 361 register 077ch: txsdq fifo cells and packets accepted aggregate count (lsb) bit type function default bit 15 to bit 0 r acount[15:0] x register 077dh: txsdq fifo cells and packets accepted aggregate count (msb) bit type function default bit 15 to bit 0 r acount[31:16] x acount[31:0]: these bits display the aggregate count of all the pos packets and atm cells that are accepted by the txsdq. this register is latched when register 0000h is written to for a global performance monitor update. after the count is latched into the register, the internal counter is reset to 0, and starts counting again. when this counter reaches it?s maximum count, it holds the value, and does not roll over.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 362 register 077eh: txsdq fifo cells and packets dropped aggregate count bit type function default bit 15 r dcount[15] x bit 14 r dcount[14] x bit 13 r dcount[13] x bit 12 r dcount[12] x bit 11 r dcount[11] x bit 10 r dcount[10] x bit 9 r dcount[9] x bit 8 r dcount[8] x bit 7 r dcount[7] x bit 6 r dcount[6] x bit 5 r dcount[5] x bit 4 r dcount[4] x bit 3 r dcount[3] x bit 2 r dcount[2] x bit 1 r dcount[1] x bit 0 r dcount[0] x dcount[15:0]: these bits display the aggregate count of all the pos packets and atm cells that are dropped by the txsdq due to fifo overflows. this register is latched when register 0000h is written to for a global performance monitor update. after the count is latched into the register, the internal counter is reset to 0, and starts counting again. when this counter reaches it?s maximum count, it holds the value, and does not roll over.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 363 register 0780h : rxphy configuration bit type function default bit 15 unused x bit 14 unused x bit 13 r/w reserved 0 bit 12 r/w reserved 0 bit 11 unused x bit 10 unused x bit 9 r/w reserved 0 bit 8 r/w reserved 0 bit 7 unused x bit 6 unused x bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w oddparity 0 bit 0 r/w rxprst 1 rxprst: the rxprst bit is used to reset the rxphy circuitry. when rxprst is set to logic zero, the rxphy operates normally. when rxprst is set to logic one, the rxphy ignores all pin inputs but the register bits may be accessed for purposes of initialization. the rxphy deasserts all outputs until a logic zero is written to rxprst. oddparity: the oddparity bit is used to set the type of parity that is generated by the rxphy for the ul3 or pos l3 interface. when set to logic 1, odd parity is generated. when set to logic 0, even parity is generated. reserved: the reserved bits must be set to logic 0 for proper operation.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 364 register 0781h : rxphy interrupt status bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r runtcelli x runtcelli in utopia, the renb was detected as being deasserted before appropriate time at end of the cell transfer. the cell will continue to be transferred as per the utopia level 3 specification, but this indicates that there may be a configuration mismatch between the rxphy and the downstream device. a possible cause is the incorrect setting of the size of the cell expected by this interface. the runtcelli bit is cleared when it is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 365 register 0782h : rxphy interrupt enable bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r/w runtcelle 0 runtcelle the runtcelle bit is used to enable runtcelli signal to assert a hardware interrupt on the intb pin. when set to logic 0, the hardware interrupt is masked. when set to logic 1, the hardware interrupt is enabled.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 366 register 0783h : rxphy indirect burst size bit type function default bit 15 r busy x bit 14 r/w config_rwb 0 bit 13 r/w phy_addr[5] 0 bit 12 r/w phy_addr[4] 0 bit 11 r/w phy_addr[3] 0 bit 10 r/w phy_addr[2] 0 bit 9 r/w phy_addr[1] 0 bit 8 r/w phy_addr[0] 0 bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w burst_size[3] 0 bit 2 r/w burst_size[2] 0 bit 1 r/w burst_size[1] 1 bit 0 r/w burst_size[0] 1 the rxphy indirect burst size register is an indirect address and data register. the register is used only in pos mode of operation. burst_size[3:0] the burst_size data register is provided to program the allowable burst size for the phy. the size of a burst is burst_size + 1. for example, a burst_size[3:0] = ?0000? indicates a burst size of one block. a block is equal to 16 bytes and takes 4 clocks to transfer. the 4 bits of burst size allow the maximum burst to be 16 blocks (256 bytes), per phy. this register is used only in pos-phy l3 mode. phy_addr[5:0] the phy_addr bits are an indirect address that is used with burst_size data. the two allow indirect address reads and writes using a small amount of external address space. the phy_addr is used with config_rwb and busy to command reads and writes. valid values for phy_addr[5:0] are from 0 to 2fh. for the s/uni-2488, phy_addr[5:0] must be set to zero. config_rwb the config_rwb register allows the indirect addressing method to specify whether a read or write is being performed. a value of ?1? means that a read is to be performed on the data
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 367 for phy_addr and will be placed in the burst_size register. a value of ?0? means that a write of the information in burst_size will be performed for phy channel address phy_addr. busy the busy bit is used in indirect addressing to indicate the the operation of read or write is currently being executed. a value of ?1? means the operation is currently in progress and the microprocessor should wait. a value of ?0? means the operation is finished and the microprocessor may proceed with further access.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 368 register 0784h : rxphy calendar length bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 r/w calendar_length[6] 0 bit 5 r/w calendar_length[5] 0 bit 4 r/w calendar_length[4] 0 bit 3 r/w calendar_length[3] 0 bit 2 r/w calendar_length[2] 0 bit 1 r/w calendar_length[1] 0 bit 0 r/w calendar_length[0] 0 calendar_length[6:0] the calendar_length register is provided to program the length of calendar used for servicing up to a maximum of 128 entries. please see the rxphy calendar indirect address data register. the number of entries is equal to calendar_length + 1. for the s/uni- 2488, this register should be set to all zeros.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 369 register 0785h : rxphy calendar indirect address data bit type function default bit 15 r busy x bit 14 r/w calendar_addr[6] 0 bit 13 r/w calendar_addr[5] 0 bit 12 r/w calendar_addr[4] 0 bit 11 r/w calendar_addr[3] 0 bit 10 r/w calendar_addr[2] 0 bit 9 r/w calendar_addr[1] 0 bit 8 r/w calendar_addr[0] 0 bit 7 r/w config_rwb 0 bit 6 unused x bit 5 r/w calendar_data[5] 0 bit 4 r/w calendar_data[4] 0 bit 3 r/w calendar_data[3] 0 bit 2 r/w calendar_data[2] 0 bit 1 r/w calendar_data[1] 0 bit 0 r/w calendar_data[0] 0 the rxphy calendar indirect address data register is an indirect address and data register. the register is used in pos mode of operation calendar_data[5:0] the calendar_data register is provided to program the phy address number to be serviced in the calendar sequence. the calendar consists of a maximum of 128 entries where the calendar_addr is used to access one of the 128 (or less) entries to either write or read calendar_data. calendar_data is the phy address to be serviced during the sequence associated with calendar_addr. the length of the calendar is set in the rxphy calendar length register. for the s/uni-2488, this register should be set to all zeros. calendar_addr[6:0] the calendar_addr register is an indirect address register that is used with calendar_data register. the two registers together allow indirect address reads and writes using a small amount of external address space. the calendar_addr is used with config_rwb and busy to command reads and writes.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 370 config_rwb the config_rwb register allows the indirect addressing method to specify whether a read or write is being performed. a value of ?1? means that a read is to be performed on the data at calendar_addr and will be placed in the calendar_data register. a value of ?0? means that a write of the information in calendar_data will be performed at address calendar_addr. busy the busy bit is used in indirect addressing to indicate the operation of read or write is currently being executed. a value of ?1? means the operation is currently in progress and the microprocessor should wait. a value of ?0? means the operation is finished and the microprocessor may proceed with further access.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 371 register 0786h : rxphy data type field bit type function default bit 15 r/w pos_field[7] 0 bit 14 r/w pos_field[6] 0 bit 13 r/w pos_field[5] 0 bit 12 r/w pos_field[4] 0 bit 11 r/w pos_field[3] 0 bit 10 r/w pos_field[2] 0 bit 9 r/w pos_field[1] 0 bit 8 r/w pos_field[0] 1 bit 7 r/w atm_field[7] 0 bit 6 r/w atm_field[6] 0 bit 5 r/w atm_field[5] 0 bit 4 r/w atm_field[4] 0 bit 3 r/w atm_field[3] 0 bit 2 r/w atm_field[2] 0 bit 1 r/w atm_field[1] 0 bit 0 r/w atm_field[0] 0 the rxphy data type field register is used in pos-phy l3 mode of operation only and is provided as a means to identify the type of traffic, atm or packet, being sent over the pos-phy l3 interface. selection of atm and packet phys is done using the pos_sel bits in the rxsdq fifo indirect configuration register. atm_field[7:0] the atm_field register is provided to identify atm cell transfers over the pos-phy l3 interface. when the outgoing data is an atm cell, then the atm_field[7:0] is inserted in rdat[31:24] at the cycle in which the in-band address is inserted in rdat[5:0] (ie. when rsx is logic 1). pos_field[7:0] the pos_field register is provided to identify packet data transfers over the pos-phy l3 interface. when the outgoing data is of type packet, then the pos_field[7:0] is inserted in rdat[31:24] at the cycle in which the in-band address is inserted in rdat[5:0] (ie. when rsx is logic 1).
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 372 register 0788h : txphy configuration bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 r/w reserved 0 bit 8 r/w reserved 0 bit 7 unused x bit 6 r/w inbandaddr 1 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w parerren 0 bit 2 r/w reserved 0 bit 1 r/w oddparity 0 bit 0 r/w txprst 1 txprst: the txprst bit is used to reset the txphy circuitry. when txprst is set to logic zero, the txphy operates normally. when txprst is set to logic one, the txphy ignores all pin inputs but the registers may be accessed for purposes of initialization. the txphy deasserts all outputs until a logic zero is written to txprst. oddparity: the oddparity bit is used to set the type of parity that is checked by the txphy. when set to logic 1, odd parity is expected. when set to logic 0, even parity is expected. this bit is global and affects all phy channels. parerren: when set to logic 1, parerren will enable the txphy to pass an error signal to the txsdq upon detection of a parity error. this will cause the packet to be aborted by the cell processor. this bit has no effect on atm cells with parity errors. inbandaddr the inbandaddr bit is used only in pos-phy l3 mode to indicate whether the in-band address is expected on the interface. this bit is useful in single phy applications where the in-band addressing is optional (address 0 is assumed) and the link layer device does not
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 373 send an address in band since there is only one phy. this bit can only be changed when txprst is logic 1. reserved: the reserved bits must be set to logic 0 for proper operation.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 374 register 0789h : txphy interrupt status bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r tdtferri x bit 1 r tparerri x bit 0 r runtcelli x runtcelli the runtcelli bit indicates that tenb was detected as being deasserted before the end of the cell transfer when operating in utopia l3 mode. this will result in a partial cell transfer and an erred cell will passed to the txsdq. possible causes are incorrect setting in the size of the cell expected by this interface. the runtcelli bit is cleared when this register is read. tparerri the tparerr bit is used to indicate that a parity error was observed on the incoming tdat bus since the last time the interrupt was read. the packet will be marked erred and sent on to the txsdq. atm cell transmission is not affected by parity errors. the tparerri bit is cleared when this register is read. tdtferri the tdtferr bit is used to indicate that a data field mismatch was observed on the incoming tdat[31:24] bus compared to the atm/packet selection for that phy configuration (selection done using the pos_sel bits in the txsdq fifo indirect configuration register). this bit is cleared on microprocessor read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 375 register 078ah : txphy interrupt enable bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w tdtferre x bit 1 r/w tparerre x bit 0 r/w runtcelle x runtcelle the runtcelle bit is used to enable the detection of the runt cell condition (runtcelli) to assert a hardware interrupt on the intb pin. when set to logic 0, the hardware interrupt is masked. when set to logic 1, the hardware interrupt is enabled. tparerre the tparerre bit is used to enable the detection of a parity error (tparerri) to assert a hardware interrupt on the intb pin. when set to logic 0, the hardware interrupt is masked. when set to logic 1, the hardware interrupt is enabled. tdtferre the tdtferre bit is used to enable the tdfterri interrupt status bit to assert a hardware interrupt on the intb pin. when set to logic 0, the hardware interrupt is masked. when set to logic 1, the hardware interrupt is enabled.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 376 register 078bh : txphy data type field bit type function default bit 15 r/w pos_field[7] 0 bit 14 r/w pos_field[6] 0 bit 13 r/w pos_field[5] 0 bit 12 r/w pos_field[4] 0 bit 11 r/w pos_field[3] 0 bit 10 r/w pos_field[2] 0 bit 9 r/w pos_field[1] 0 bit 8 r/w pos_field[0] 1 bit 7 r/w atm_field[7] 0 bit 6 r/w atm_field[6] 0 bit 5 r/w atm_field[5] 0 bit 4 r/w atm_field[4] 0 bit 3 r/w atm_field[3] 0 bit 2 r/w atm_field[2] 0 bit 1 r/w atm_field[1] 0 bit 0 r/w atm_field[0] 0 the txphy data type field is used in pos-phy l3 mode of operation only and is provided as a means to identify the type of traffic, atm or packet, being sent over the pos-phy l3 interface. selection of atm and packet phys is done using the pos_sel bit in the txsdq fifo indirect configuration register. atm_field[7:0] the atm_field register is provided to identify an atm cell being transferred over the pos- phy l3 interface. when the incoming data is of type atm cell, then the value of tdat[31:24] at the cycle in which the in-band address is inserted on tdat[5:0] (ie. when tsx = 1) should match atm_field[7:0]. otherwise, an interrupt is signaled to indicate a data type mismatch. pos_field[7:0] the pos_field register is provided to identify packet data being transferred over the pos- phy l3 interface. when the incoming data is of type packet, then the value of tdat[31:24] at the cycle in which the in-band address is inserted on tdat[5:0] (ie. when tsx = 1) should match pos_field[7:0]. otherwise, an interrupt is signaled to indicate a data type mismatch.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 377 register 0790h: sirp configuration timeslot bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 r/w tsx_rdi[1] 0 bit 10 r/w tsx_rdi[0] 0 bit 9 r/w tsx_rei[3] 0 bit 8 r/w tsx_rei[2] 0 bit 7 r/w tsx_rei[1] 0 bit 6 r/w tsx_rei[0] 0 bit 5 r/w tsx_force_lcd 0 bit 4 r/w tsx_rdi20f 0 bit 3 r/w tsx_erdi 0 bit 2 r/w tsx_rmode[1] 1 bit 1 r/w tsx_rmode[0] 1 bit 0 r/w tsx_prov 0 tsx_prov: when tsx_prov is logic 0, automatic remote alarm reporting is disabled for the aps in bus into the thpp. when tsx_prov is logic 1, automatic remote alarm reporting is enabled for the aps in data stream to the thpp. tsx_rmode[1:0]: the tsx_rmode[1:0] bits identify the mode of reporting sts path remote defect indications (rdi) as shown in table 13.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 378 table 13: sirp rdi and rei reporting modes tsx_rmode[1:0] error reporting mode 00 register mode: source rei[3:0] and rdi[1:0] from internal registers tsx_rei[3:0] and tsx_rdi[1:0] respectively. the remote alarm port and lcd indications (which map to a specified 2 bit programmable rdi code) are ignored. 01 remote alarm input only mode: source rei[3:0] and rdi[1:0] entirely from the aps in bus. 10 remote alarm input with loss of atm cell delineation input mode: source rei[3:0] from the aps in bus and rdi[1:0] from lcd indications with a specified 2 bit rdi code. 11 normal error reporting mode: source rei[3:0] from the aps in bus. lcd indications with a specified 2-bit rdi code is compared to incoming rdi[1:0] from the aps in bus. higher priority rdi takes precedence. tsx_erdi: the tsx_erdi bit selects between normal and extended rdi encoding. when tsx_erdi is set high, extended rdi is selected. the rdi output is treated as a 2-bit codepoint. when tsx_erdi is set low, normal rdi is selected. these selections are summarized in table 14. table 14: sirp rdi settings ts x _rdi[1:0] erdi interpretation 00 no rdi-p defect 01 erdi-p payload defect 10 erdi-p server defect tsx_erdi = 1 11 erdi-p connectivity defect 00 no rdi-p defect 01 no rdi-p defect 10 rdi-p defect tsx_erdi = 0 11 rdi-p defect
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 379 tsx_rdi20f: the tsx_rdi20f bits specify the configuration of rdi maintenance duration. the standard required duration is 10 frames. the gr-253 objective duration is 20 frames. the two options are specified by the tsx_rdi20f bit are selected as shown in table 15. table 15: sirp rdi maintenance ts x _rdi20f configuration 0 a particular rdi value for will be maintained for the required 10 frames before changing to a lower priority rdi code. 1 a particular rdi value for will be maintained for the gr-253 objective 20 frames before changing to a lower priority rdi code. tsx_force_lcd: the tsx_force_lcd bit is used to force a loss of atm cell delineation (lcd) event. a logic or operation is performed on the lcd indication and the tsx_force_lcd bit. when tsx_force_lcd is set high, an lcd event is assumed and rdi[1:0] is sourced entirely from a specified 2 bit rdi code (lcd[1:0]). the tsx_force_lcd bit is ignored when tsx_rmode[1:0] = b?00 and b?01. tsx_rei[3:0]: the tsx_rei[3:0] bits are used to manually transmit an sts path remote error indication (rei) when both tsx_rmode[1:0] register bits are set low. if tsx_rei[3:0] is 0, far end block errors are automatically reported to the transmit data stream (if tsx_prov = 1). if tsx_rei[3:0] is set to a value other than 0, then that value will be transmitted at the next opportunity. after the transmission is completed, tsx_rei[3:0] is reset to the value 0. tsx_rdi[1:0]: the tsx_rdi[1:0] bits control the value of the rdi output of the data stream selected when both tsx_rmode[1:0] register bits are set low. when extended rdi is enabled (tsx_erdi set high), the rdi output is controlled directly by tsx_rdi [1:0] register bits when either register bit is set high. the rdi output reflects the remote alarm status (if tsx_prov = 1) when both tsx_rdi[1:0] register bits are set low. when extended rdi is disabled (tsx_erdi set low), and the rdi[0] register bit is set high, the rdi output is forced high regardless of the remote alarm status. when rdi[0] is set low, the rdi output reflects the remote alarm status. when both tsx_rmode[1:0] register bits are not set low, the tsx_rdi[1:0] bits are ignored.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 380 register 079ch: sirp configuration bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 r/w rdiprihi[1] 0 bit 4 r/w rdiprihi[0] 0 bit 3 r/w rdiprimid[1] 0 bit 2 r/w rdiprimid[0] 0 bit 1 r/w lcd[1] 1 bit 0 r/w lcd[0] 0 lcd[1:0]: the lcd[1:0] bits represent the 2 bit programmable rdi code generated when a loss of atm cell delineation (lcd) event is detected. rdiprimid[1:0] the rdiprimid[1:0] bits specify which two-bit alarm code point (rdi) will be treated as the second highest priority code. these bits combined with the rdiprihi bits allow almost any priority scheme to be specified. the bits are interpreted as shown in rdiprihi[1:0] the rdiprihi[1:0] bits specify which two-bit alarm code point (rdi) will be treated as the highest priority code. high priority codes will replace low priority codes at the next transmit g1 byte, instead of allowing 10/20 copies to be sent. the highest priority alarm is sent 10/20 times before replacement is allowed. table 16. rdiprihi[1:0] the rdiprihi[1:0] bits specify which two-bit alarm code point (rdi) will be treated as the highest priority code. high priority codes will replace low priority codes at the next transmit g1 byte, instead of allowing 10/20 copies to be sent. the highest priority alarm is sent 10/20 times before replacement is allowed.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 381 table 16: sirp rdi priority schemes priority of codes (3 = highest) rdiprihi[1:0] rdiprimid[1:0] code priority 11 3 01 2 10 1 11 01 00 0 11 3 10 2 01 1 11 10 00 0 10 3 11 2 01 1 10 11 00 0 10 3 01 2 11 1 10 01 00 0 01 3 11 2 10 1 01 11 00 0 01 3 10 2 11 1 01 10 00 0 11 1 10 1 01 1 00 00 00 0 other codes other codes reserved note: when rdiprihi[1:0] and rdiprimid[1:0] are both equal to b?00, all rdi codes have equal priority except rdi[1:0] = b?00 which always has lowest priority.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 382 register 0800h: prgm indirect address register 0810h: prgm aux 2 indirect address register 0820h: prgm aux 3 indirect address register 0830h: prgm aux 4 indirect address bit type function default bit 15 r busy x bit 14 r/w rwb 0 bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 r/w iaddr[3] 0 bit 8 r/w iaddr[2] 0 bit 7 r/w iaddr[1] 0 bit 6 r/w iaddr[0] 0 bit 5 unused x bit 4 unused x bit 3 r/w path[3] 0 bit 2 r/w path[2] 0 bit 1 r/w path[1] 0 bit 0 r/w path[0] 0 path[3:0]: the sts-1/stm-0 path (path[3:0]) bits select which sts-1/stm-0 path is accessed by the current indirect transfer. for the s/uni-2488, path[3:0] should be set to 1h. iaddr[3:0]: the internal address bits select which internal register is accessed by the current indirect transfer. six registers are defined for the monitor while four pages are defined for the generator. iaddr[3:0] register 0000 monitor - timeslot configuration page 0001 monitor - prbs[22:7] page 0010 monitor - prbs[6:0] page 0011 monitor - b1/e1 value page
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 383 0100 monitor - monitor error count page 0101 monitor - received b1 and e1 1000 generator - timeslot configuration page 1001 generator - prbs[22:7] page 1010 generator - prbs[6:0] page 1011 generator - b1/e1 value page rw b: the active high read and active low write (rwb) bit selects if the current access to the internal register is an indirect read or an indirect write. writing to the indirect address register initiates an access to the internal register. when rwb is set to logic 1, an indirect read access to the register is initiated. the data from the addressed location in the internal register will be transfer to the indirect data register. when rwb is set to logic 0, an indirect write access to the register is initiated. the data from the indirect data register will be transfer to the addressed location in the internal register. busy: the active high ram busy (busy) bit reports if a previously initiated indirect access to the internal register has been completed. busy is set to logic 1 upon writing to the indirect address register. busy is set to logic 0, upon completion of the ram access. this register should be polled to determine when new data is available in the indirect data register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 384 register 0801h: prgm indirect data register 0811h: prgm aux 2 indirect data register 0821h: prgm aux 3 indirect data register 0831h: prgm aux 4 indirect data bit type function default bit 15 r/w data[15] 0 bit 14 r/w data[14] 0 bit 13 r/w data[13] 0 bit 12 r/w data[12] 0 bit 11 r/w data[11] 0 bit 10 r/w data[10] 0 bit 9 r/w data[9] 0 bit 8 r/w data[8] 0 bit 7 r/w data[7] 0 bit 6 r/w data[6] 0 bit 5 r/w data[5] 0 bit 4 r/w data[4] 0 bit 3 r/w data[3] 0 bit 2 r/w data[2] 0 bit 1 r/w data[1] 0 bit 0 r/w data[0] 0 data[15:0]: the indirect access data (data[15:0]) bits hold the data transfer to or from an internal register during indirect access. when rwb is set to logic 1 (indirect read), the data from the addressed location in the internal register will be transfer to data[15:0]. busy should be polled to determine when the new data is available in data[15:0]. when rwb is set to logic 0 (indirect write), the data from data[15:0] will be transfered to the addressed location in the internal register. the indirect data register must contain valid data before the indirect write is initiated by writing to the indirect address register. data[15:0] has a different meaning depending on which internal register is being accessed.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 385 register 0802h: prgm generator payload configuration register 0812h: prgm aux 2 generator payload configuration register 0822h: prgm aux 3 generator payload configuration register 0832h: prgm aux 4 generator payload configuration bit type function default bit 15 r/w gen_sts12csl 0 bit 14 r/w gen_sts12c 0 bit 13 unused x bit 12 unused x bit 11 unused x bit 10 r/w gen_msslen[2] 0 bit 9 r/w gen_msslen[1] 0 bit 8 r/w gen_msslen[0] 0 bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w reserved 0 gen_msslen[2:0], gen_sts12c, gen_sts12csl: these bits control the operating mode of the prgm generators. the bits should be set according to the table below. prgm gen_sts12c gen_sts12csl gen_msslen[2:0] master 1 0 011 aux2 aux3 aux4 11 011
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 386 register 0803h: prgm monitor payload configuration register register 0813h: prgm aux 2 monitor payload configuration register 0823h: prgm aux 3 monitor payload configuration register 0833h: prgm aux 4 monitor payload configuration bit type function default bit 15 r/w mon_sts12csl 0 bit 14 r/w mon_sts12c 0 bit 13 unused x bit 12 unused x bit 11 unused x bit 10 r/w mon_msslen[2] 0 bit 9 r/w mon_msslen[1] 0 bit 8 r/w mon_msslen[0] 0 bit 7 unused x bit 6 r/w reserved 0 bit 5 unused x bit 4 unused x bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w reserved 0 mon_msslen[2:0], mon_sts12c, mon_sts12csl: these bits control the operating mode of the prgm monitors. the bits should be set according to the table below. prgm mon_sts12c mon_sts12csl mon_msslen[2:0] master 1 0 011 aux2 aux3 aux4 11 011
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 387 register 0804h: prgm monitor byte error interrupt status register 0814h: prgm aux 2 monitor byte error interrupt status register 0824h: prgm aux 3 monitor byte error interrupt status register 0834h: prgm aux 4 monitor byte error interrupt status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r mon[n+12]_erri x bit 10 r mon[n+11]_erri x bit 9 r mon[n+10]_erri x bit 8 r mon[n+9]_erri x bit 7 r mon[n+8]_erri x bit 6 r mon[n+7]_erri x bit 5 r mon[n+6]_erri x bit 4 r mon[n+5]_erri x bit 3 r mon[n+4]_erri x bit 2 r mon[n+3]_erri x bit 1 r mon[n+2]_erri x bit 0 r mon[n+1]_erri x mon x _erri: the monitor byte error interrupt status registers contain the status of the interrupt generated by each of the 48 sts-1 paths when an error has been detected. prgm monitor byte error interrupt status register, n = 0. prgm aux2 monitor byte error interrupt status register, n = 1. prgm aux3 monitor byte error interrupt status register, n = 2. prgm aux4 monitor byte error interrupt status register, n = 3. the mon x _erri bit is set high when the monitor is in the synchronized state and when an error in a prbs byte is detected in the sts-1 path x . this bit is independent of mon x _erre, and is cleared after it?s been read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 388 register 0805h: prgm monitor byte error interrupt enable register 0815h: prgm aux 2 monitor byte error interrupt enable register 0825h: prgm aux 3 monitor byte error interrupt enable register 0835h: prgm aux 4 monitor byte error interrupt enable bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r/w mon[n+12]_erre 0 bit 10 r/w mon[n+11]_erre 0 bit 9 r/w mon[n+10]_erre 0 bit 8 r/w mon[n+9]_erre 0 bit 7 r/w mon[n+8]_erre 0 bit 6 r/w mon[n+7]_erre 0 bit 5 r/w mon[n+6]_erre 0 bit 4 r/w mon[n+5]_erre 0 bit 3 r/w mon[n+4]_erre 0 bit 2 r/w mon[n+3]_erre 0 bit 1 r/w mon[n+2]_erre 0 bit 0 r/w mon[n+1]_erre 0 mon x _erre: the monitor byte error interrupt enable registers enable the interrupt for each of the 48 sts- 1 paths. prgm monitor byte error interrupt enable register, n = 0. prgm aux2 monitor byte error interrupt enable register, n = 1. prgm aux3 monitor byte error interrupt enable register, n = 2. prgm aux4 monitor byte error interrupt enable register, n = 3. when mon x _erre is set high, the byte error interrupt is allowed to generate an interrupt on intb.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 389 register 0806h: monitor b1/e1 bytes interrupt status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r reserved x bit 10 r reserved x bit 9 r reserved x bit 8 r reserved x bit 7 r reserved x bit 6 r reserved x bit 5 r reserved x bit 4 r reserved x bit 3 r reserved x bit 2 r reserved x bit 1 r reserved x bit 0 r mon1_b1e1i x mon1_b1e1i: the mon1_b1e1i bit indicates the status of the interrupt generated when a change in the status of the comparison has been detected on the b1/e1 bytes. the mon1_b1e1i is set high when the monitor is in the synchronized state and when the status change is detected on either the b1 or e1 bytes. for example, if a mismatch is detected and the previous comparison was a match, the mon1_b1e1i bit will be set high. but if a mismatch is detected and the previous comparison was a mismatch, the mon1_b1e1i bit will keep its previous value. this bit is independent of mon1_b1e1e, and is cleared after it?s been read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 390 register 0807h: monitor b1/e1 bytes interrupt enable bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r/w reserved 0 bit 10 r/w reserved 0 bit 9 r/w reserved 0 bit 8 r/w reserved 0 bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w mon1_ b1e1e 0 mon1_b1e1e: when mon1 _ b1e1e is set high, the b1/e1bytes interrupt (mon1_b1e1i ) is allowed to generate an interrupt on intb.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 391 register 0808h: monitor b1/e1 bytes status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r reserved x bit 10 r reserved x bit 9 r reserved x bit 8 r reserved x bit 7 r reserved x bit 6 r reserved x bit 5 r reserved x bit 4 r reserved x bit 3 r reserved x bit 2 r reserved x bit 1 r reserved x bit 0 r mon1_ b1e1v x mon1_b1e1v: the monitor b1/e1 bytes status value bit reflects the status of the previous b1/e1 comparison. when mon1 _ b1e1v is set high, an error on the previous b1 or e1 bytes has been detected. when mon1 _ b1e1v is low, the received b1 and e1 bytes were the expected ones.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 392 register 0809h: prgm monitor synchronization interrupt status register 0819h: prgm aux 2 monitor synchronization interrupt status register 0829h: prgm aux 3 monitor synchronization interrupt status register 0839h: prgm aux 4 monitor synchronization interrupt status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r mon[n+12]_synci x bit 10 r mon[n+11]_synci x bit 9 r mon[n+10]_synci x bit 8 r mon[n+9]_synci x bit 7 r mon[n+8]_synci x bit 6 r mon[n+7]_synci x bit 5 r mon[n+6]_synci x bit 4 r mon[n+5]_synci x bit 3 r mon[n+4]_synci x bit 2 r mon[n+3]_synci x bit 1 r mon[n+2]_synci x bit 0 r mon[n+1]_synci x mon x _synci: the monitor synchronization interrupt status registers indicate synchronization interrupts for each of the 48 sts-1 paths. prgm monitor synchronization interrupt status register, n = 0. prgm aux2 monitor synchronization interrupt status register, n = 1. prgm aux3 monitor synchronization interrupt status register, n = 2. prgm aux4 monitor synchronization interrupt status register, n = 3. the monitor synchronization interrupt status interrupt (mon x _synci) bit is set high when a change occures in the monitor?s synchronization status. whenever a state machine of the x sts-1 path goes from synchronized to out of synchronization state or vice-versa, the mon x _synci is set high. this bit is independent of monx_synce, and is cleared after it?s been read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 393 register 080ah: prgm monitor synchronization interrupt enable register 081ah: prgm aux 2 monitor synchronization interrupt enable register 082ah: prgm aux 3 monitor synchronization interrupt enable register 083ah: prgm aux 4 monitor synchronization interrupt enable bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r/w mon[n+12]_synce 0 bit 10 r/w mon[n+11]_synce 0 bit 9 r/w mon[n+10]_synce 0 bit 8 r/w mon[n+9]_synce 0 bit 7 r/w mon[n+8]_synce 0 bit 6 r/w mon[n+7]_synce 0 bit 5 r/w mon[n+6]_synce 0 bit 4 r/w mon[n+5]_synce 0 bit 3 r/w mon[n+4]_synce 0 bit 2 r/w mon[n+3]_synce 0 bit 1 r/w mon[n+2]_synce 0 bit 0 r/w mon[n+1]_synce 0 mon x _synce: the monitor synchronization interrupt enable registers enables the synchronization interrupts for each of the 48 sts-1 paths. prgm monitor synchronization interrupt enable register, n = 0. prgm aux2 monitor synchronization interrupt enable register, n = 1. prgm aux3 monitor synchronization interrupt enable register, n = 2. prgm aux4 monitor synchronization interrupt enable register, n = 3. the monitor synchronization interrupt enable register allows each individual sts-1 path to generate an external interrupt on intb. when mon x _synce is set high, a change in the synchronization state of the monitor in sts-1 path x generates an interrupt on intb.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 394 register 080bh: prgm monitor synchronization status register 081bh: prgm aux 2 monitor synchronization status register 082bh: prgm aux 3 monitor synchronization status register 083bh: prgm aux 4 monitor synchronization status bit type function default bit 15 unused bit 14 unused bit 13 unused bit 12 unused bit 11 r mon[n+12]_syncv x bit 10 r mon[n+11]_syncv x bit 9 r mon[n+10]_syncv x bit 8 r mon[n+9]_syncv x bit 7 r mon[n+8]_syncv x bit 6 r mon[n+7]_syncv x bit 5 r mon[n+6]_syncv x bit 4 r mon[n+5]_syncv x bit 3 r mon[n+4]_syncv x bit 2 r mon[n+3]_syncv x bit 1 r mon[n+2]_syncv x bit 0 r mon[n+1]_syncv x mon x _syncv: the monitor synchronization status registers reflects the synchronization state of each sts-1 path. prgm monitor synchronization status register, n = 0. prgm aux2 monitor synchronization status register, n = 1. prgm aux3 monitor synchronization status register, n = 2. prgm aux4 monitor synchronization status register, n = 3. the monitor synchronization status registers reflect the state of the monitor?s state machine. when mon x _syncv is set high, the monitor?s state machine is in synchronization for the sts-1 path x . when mon x _syncv is low, the monitor is out of sync for the sts-1 path x .
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 395 indirect register 0800h: prgm monitor timeslot configuration page bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 r/w reserved 0 bit 9 r/w reserved 0 bit 8 unused x bit 7 unused x bit 6 r/w seq_prbsb 0 bit 5 r/w b1e1_ena 0 bit 4 unused x bit 3 w resync 0 bit 2 r/w inv_prbs 0 bit 1 r/w reserved 0 bit 0 r/w mon_ena 0 mon_ena: monitor enable register bit enables the prbs monitors for the prgm blocks (all 48). if mon_ena is set high, a prbs sequence is generated and compare to the incoming one inserted in the payload of the sonet/sdh frame. if mon_ena is low, the data at the input of the monitor is ignored. inv_prbs: sets the monitor to invert the prbs before comparing it to the internally generated payload. when set high, the prbs bytes will be inverted else they will be compared unmodified. resync: sets the monitor to re-initialize the prbs sequence. when set high, the monitor?s state machines will be forced in the out of sync state and automatically try to resynchronize to the incoming stream. to force another resynchronization, the bit needs to be set low again before it is set high.. b1e1_ena: when high, this bit enables the monitoring of the b1 and e1 bytes in the sonet/sdh frame. the incoming b1 byte is compared to a programmable register. the e1 byte is compared to
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 396 the complement of the same value. when b1e1_ena is high, the b1 and e1 bytes are monitored. seq_prbsb: this bit enables the monitoring of a prbs or sequential pattern inserted in the payload. when low, the payload is expected to contain prbs bytes. when high, the payload is expected to contain a sequential pattern. reserved: the reserved bit should be set to logic 0 for proper operation.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 397 indirect register 0801h: prgm monitor prbs[22:7] accumulator page bit type function default bit 15 to bit 0 r/w prbs[22:7] 0000 indirect register 0802h: prgm monitor prbs[6:0] accumulator page bit type function default bit 15 to bit 7 unused 00 bit 6 to bit 0 r/w prbs[6:0] 00 prbs[22:0]: the prbs[22:0] register contians the state of the lfsr monitor. it is possible to write in this register to change the initial state of the monitor.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 398 indirect register 0803h: prgm monitor b1/e1 value page bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 r/w b1[7] 0 bit 6 r/w b1[6] 0 bit 5 r/w b1[5] 0 bit 4 r/w b1[4] 0 bit 3 r/w b1[3] 0 bit 2 r/w b1[2] 0 bit 1 r/w b1[1] 0 bit 0 r/w b1[0] 0 this indirect register is not valid for prgm aux2, aux3, aux4. b1[7:0]: when enabled, the monitoring of the b1byte in the incoming sonet/sdh frame is a simple comparison to the value in the prgm monitor b1/e1 value page register. the same value is used for the monitoring of the e1 byte except its complement is used.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 399 indirect register 0804h: prgm monitor error count page bit type function default bit 15 r err_cnt[15] x bit 14 r err_cnt[14] x bit 13 r err_cnt[13] x bit 12 r err_cnt[12] x bit 11 r err_cnt[11] x bit 10 r err_cnt[10] x bit 9 r err_cnt[9] x bit 8 r err_cnt[8] x bit 7 r err_cnt[7] x bit 6 r err_cnt[6] x bit 5 r err_cnt[5] x bit 4 r err_cnt[4] x bit 3 r err_cnt[3] x bit 2 r err_cnt[2] x bit 1 r err_cnt[1] x bit 0 r err_cnt[0] x err_cnt[15:0]: the err_cnt[15:0] register is the number of error in the prbs bytes detected during the monitoring. errors are accumulated only when the monitor is in the synchonized state. even if there are multiple errors within one prbs byte, only one error is counted. the transfer of the error counter to this holding register is trigger by an indirect write to this register or writing register 0000h for a global performance monitor update. the error counter will not wrap around after reaching ffffh. it will saturate to this value.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 400 indirect register 0805h: prgm monitor received b1/e1 bytes page bit type function default bit 15 r rec_e1[7] x bit 14 r rec_e1[6] x bit 13 r rec_e1[5] x bit 12 r rec_e1[4] x bit 11 r rec_e1[3] x bit 10 r rec_e1[2] x bit 9 r rec_e1[1] x bit 8 r rec_e1[0] x bit 7 r rec_b1[7] x bit 6 r rec_b1[6] x bit 5 r rec_b1[5] x bit 4 r rec_b1[4] x bit 3 r rec_b1[3] x bit 2 r rec_b1[2] x bit 1 r rec_b1[1] x bit 0 r rec_b1[0] x this indirect register is not valid for prgm aux2, aux3, aux4. rec_b1[7:0]: the received b1 byte is the content of the b1 byte position in the sonet/sdh frame. every time a b1 byte is received, it is copied in this register. rec_e1[7:0]: the received e1 byte is the content of the e1 byte position in the sonet/sdh frame. every time a e1 byte is received, it is copied in this register.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 401 indirect register 0808h: prgm generator timeslot configuration page bit type function default bit 15 unused x bit 14 unused x bit 13 r/w reserved 0 bit 12 r/w prbs_ena 0 bit 11 unused x bit 10 unused x bit 9 r/w reserved 0 bit 8 r/w reserved 0 bit 7 r/w s[1] 0 bit 6 r/w s[0] 0 bit 5 r/w prbs_seqb 1 bit 4 r/w b1e1_ena 0 bit 3 w force_err 0 bit 2 unused x bit 1 r/w inv_prbs 0 bit 0 r/w reserved 0 inv_prbs: sets the generator to invert the prbs before inserting it in the payload. when set high, the prbs bytes will be inverted; else they will be inserted unmodified. force_err: the force error bit is used to force bit errors in the inserted pattern. when set high, the msb of the next byte will be inverted, inducing a single bit error. the register will clear itself when the operation is complete. a read operation will always result in a logic ?0?. b1e1_ena: this bit enables the replacement of the b1 byte in the sonet/sdh frame, by a programmable value. the e1 byte is replaced by the complement of the same value. when b1e1_ena is high, the b1 and e1 bytes are replaced in the frame; otherwise they go through the prgm unaltered. prbs_seqb: this bit enables the insertion of a prbs sequence or a sequential pattern in the payload. when high, the payload is filled with prbs bytes. when low, a sequential pattern is inserted.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 402 s[1:0]: the s[1:0] bits contain the value inserted in the s[1:0] bit positions in the payload pointer. reserved: the reserved bit should be set to logic 0 for proper operation. prbs_ena: this bit specifies if prbs overwriting is enabled. if prbs_ena is high, prbs patterns are generated and are used to overwrite the data stream; else no pattern is generated and the data stream is not overwritten. reserved: the reserved bit should be programmed to logic 0 for proper operation.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 403 indirect register 0809h : prgm generator prbs[22:7] accumulator page bit type function default bit 15 to bit 0 r/w prbs[22:7] 0000 indirect register 080ah: prgm generator prbs[6:0] accumulator page bit type function default bit 15 to bit 7 unused 00 bit 6 to bit 0 r/w prbs[6:0] 00 prbs[22:0]: the prbs[22:0] register contians the state of the lfsr generator. it is possible to write in this register to change the initial state of the monitor.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 404 indirect register 080bh: prgm generator b1/e1 value page bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 r/w b1[7] 0 bit 6 r/w b1[6] 0 bit 5 r/w b1[5] 0 bit 4 r/w b1[4] 0 bit 3 r/w b1[3] 0 bit 2 r/w b1[2] 0 bit 1 r/w b1[1] 0 bit 0 r/w b1[0] 0 this indirect register is not valid for prgm aux2, aux3, aux4. b1[7:0]: when enabled, the value in this register is inserted in the b1byte position of the outgoing sonet/sdh frame. the complement of this value is also inserted at the e1 byte position.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 405 register 0840h: r8td aps1 control and status register 0848h: r8td aps2 control and status register 0850h: r8td aps3 control and status register 0858h: r8td aps4 control and status bit type function default bit 15 r/w dlben 0 bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 r/w pininv 0 bit 8 r/w ofaais 0 bit 7 r/w fuoe 0 bit 6 r/w lcve 0 bit 5 r/w ofae 0 bit 4 r/w ocae 0 bit 3 r ofav x bit 2 r ocav x bit 1 w fofa x bit 0 w foca x foca: the force out-of-character-alignment bit (foca) controls the operation of the character alignment circuit on a serial link. a transition from logic zero to logic one in this bit forces the receiver to the out-of-character-alignment state where it will search for the transport frame alignment character (k28.5). this bit must be manually set to logic zero before it can be used again. fofa: the force out-of-frame-alignment bit (fofa) controls the operation of the frame alignment circuit. a transition from logic zero to logic one in this bit forces the receiver to the out-of- frame-alignment state where it will search for the transport frame alignment character (k28.5). this bit must be manually set to logic zero before it can be used again.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 406 ocav: the out-of-character-alignment status bit (ocav) reports the state of the character alignment circuit. ocav is set high when the receiver is in the out-of-character-alignment state. ocav is set low when the receiver is in the in-character-alignment state. ofav the out-of-frame-alignment status bit (ofav) reports the state of the frame alignment circuit. ofav is set high when the receiver is in the out-of-frame-alignment state. ofav is set low when the receiver is in the in-frame-alignment state. ocae: the out-of-character-alignment interrupt enable bit (ocae) controls the change of character alignment state interrupts. interrupts may be generated when the character alignment circuit changes state to the out-of-character-alignment state or to the in-character-alignment state. when ocae is set high, an interrupt is generated when a change of state occurs. interrupts due to changes of character alignment state are masked when ocae is set low. ofae the out-of-frame-alignment interrupt enable bit (ofae) controls the change of frame alignment state interrupts. interrupts may be generated when the frame alignment block changes state to the out-of-frame-alignment state or to the in-frame-alignment state. when ofae is set high, an interrupt is generated when a change of state occurs. interrupts due to changes of frame alignment state are masked when ofae is set low. lcve: the line code violation interrupt enable bit (lcve) controls the line code violation event interrupts. interrupts may be generated when a line code violation is detected. when lcve is set high, an interrupt is generated when an lcv is detected. interrupts due of lcvs are masked when lcve is set low. fuoe the fifo underrun/overrun status interrupt enable (fuoe) controls the underrun/overrun event interrupts. interrupts may be generated when the underrun/overrun event is detected. when fuoe is set high, an interrupt is generated when a fifo underrun or overrun condition is detected. interrupts due to fifo underrun of overrun conditions are masked when fueo is set low. ofaais the out of frame alignment alarm indication signal (ofaais) is set high to force high-order ais signals in the r8td egress data stream if the r8td is in the out-of-frame-alignment state. the r8td egress data stream is left unaffected in the out-of-frame alignment state when the offais is set low.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 407 pininv the parallel incoming data invert bit (pininv) controls the active polarity of the incoming data stream. when pininv is set high, the incoming data stream is complemented before further processing by the r8td. when pininv is set low, the incoming data stream is not complemented. dlben: the diagnostic loopback enable bit (dlben) controls diagnostic loopback operation. when dlben is set high, serial telecombus diagnostic loopback is enabled. when dlben is set low, serial telecombus diagnostic loopback is disabled. the loopback involves the complementary r8td and t8te blocks. for example, the t8te which sources apso[1] will be diagnostically looped back to the r8td which sinks apsi[1].
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 408 register 0841h: r8td aps1 interrupt status register 0849h: r8td aps2 interrupt status register 0851h: r8td aps3 interrupt status register 0859h: r8td aps4 interrupt status bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 r fuoi x bit 6 r lcvi x bit 5 r ofai x bit 4 r ocai x bit 3 unused x bit 2 unused x bit 1 unused 0 bit 0 unused x ocai: the out-of-character-alignment interrupt status bit (ocai) reports and acknowledges change of character alignment state interrupts. interrupts are generated when the character alignment block changes state to the out-of-character-alignment state or to the in-character- alignment state. ocai is set high when change of state occurs and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. when the interrupt is masked by the ocae bit the ocai remains valid and may be polled to detect change of frame alignment events. ofai the out-of-frame-alignment interrupt status bit (ofai) reports and acknowledges change of frame alignment state interrupts. interrupts are generated when the frame alignment block changes state to the out-of-frame-alignment state or to the in-frame-alignment state. ofai is set high when change of state occurs and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. when the interrupt is masked by
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 409 the ofae bit the ofai remains valid and may be polled to detect change of frame alignment events. lcvi: the line code violation event interrupt status bit (lcvi) reports and acknowledges line code violation interrupts. interrupts are generated when the character alignment block detects a line code violation in the incoming data stream. lcvi is set high when a line code violation event is detected and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. when the interrupt is masked by the lcve bit the lcvi remains valid and may be polled to detect change of frame alignment events. fuoi the fifo underrun/overrun event interrupt status bit (fuoi) reports and acknowledges the fifo underrun/overrun interrupts. interrupts are generated when the character alignment block detects a that the read and write pointers are within one of each other. fuoi is set high when this event is detected and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. when the interrupt is masked by the fuoe bit the fuoi remains valid and may be polled to detect underrun/overrun events.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 410 register 0842h: r8td aps1 line code violation count register 084ah: r8td aps2 line code violation count register 0852h: r8td aps3 line code violation count register 085ah: r8td aps4 line code violation count bit type function default bit 15 r lcv[15] x bit 14 r lcv[14] x bit 13 r lcv[13] x bit 12 r lcv[12] x bit 11 r lcv[11] x bit 10 r lcv[10] x bit 9 r lcv[9] x bit 8 r lcv[8] x bit 7 r lcv[7] x bit 6 r lcv[6] x bit 5 r lcv[5] x bit 4 r lcv[4] x bit 3 r lcv[3] x bit 2 r lcv[2] x bit 1 r lcv[1] x bit 0 r lcv[0] x lcv[15:0]: the lcv[15:0] bits reports the number of line code violations that have been detected since the last time the lcv registers were polled. the lcv registers are polled by writing to this register or to register 0000h, the s/uni-2488 identity, and global performance monitor update. this action transfers the internally accumulated error count to the lcv registers within 5 refclk cycles and simultaneously resets the internal counter to begin a new cycle of error accumulation.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 411 register 0843h: r8td aps1 analog control 1 register 084bh: r8td aps2 analog control 1 register 0853h: r8td aps3 analog control 1 register 085bh: r8td aps4 analog control 1 bit type function default bit 15 r/w reserved 1 bit 14 r/w reserved 1 bit 13 r/w reserved 1 bit 12 r/w reserved 1 bit 11 r/w reserved 0 bit 10 r/w reserved 1 bit 9 r/w reserved 0 bit 8 r/w reserved 0 bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 unused x this register controls internal analog functions. reserved[8:0] the reserved[8:0] bits must be set to the indicated default value for correct operation of the tse.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 412 register 0844h: r8td aps1 analog control 2 register 084ch: r8td aps2 analog control 2 register 0854h: r8td aps3 analog control 2 register 085ch: r8td aps4 analog control 2 bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 r reserved x bit 8 r reserved x bit 7 r reserved x bit 6 r reserved x bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w reserved 0 this register controls internal analog functions. this register should not be used.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 413 register 0860h: t8te aps1 control and status register 0868h: t8te aps2 control and status register 0870h: t8te aps3 control and status register 0878h: t8te aps4 control and status bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 r/w reserved 0 bit 4 r/w fifoerre 0 bit 3 r/w tpins 0 bit 2 r/w llben 0 bit 1 w center 1 bit 0 r/w dlcv 0 dlcv: the diagnose line code violation bit (dlcv) controls the insertion of line code violation in the outgoing data stream. when this bit is set high, the transmit encoded data bus is inverted to generate the complementary running disparity. center: the fifo centering control bit (center) controls the separation of the fifo read and write pointers. center is a write only bit. when a logic high is written to center, and the current fifo depth is not in the range of 3, 4 or 5 characters, the fifo depth is forced to be four 8b/10b characters deep, with a momentary data corruption. writing to the center bit when the fifo depth is in the 3, 4 or 5 character range produces no effect. center always returns a logic low when read. llben: the line loopback enable bit (llben) controls line loopback operation. when llben is set high, serial line loopback is enabled. when llben is set low, line loopback is disabled.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 414 tpins: the test pattern insertion (tpins) controls the insertion of test pattern in the outgoing data stream for jitter testing purpose. when this bit is set high, the test pattern stored in the registers (tp[9:0]) is used to replace all the overhead and payload bytes of the output data stream. when tpins is set low, no test patterns are generated. fifoerre: the fifo overrun/underrun error interrupt enable bit (fifoerre) controls the fifo overrun interrupt event. an interrupt is generated on a fifo error event if the fifoerre is set to logic 1. no interrupt is generated if fifoerre if is set to logic 0.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 415 register 0861h: t8te aps1 interrupt status register 0869h: t8te aps2 interrupt status register 0871h: t8te aps3 interrupt status register 0879h: t8te aps4 interrupt status bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r fifoerri x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 unused x fifoerri: the fifo overrun/underrun error interrupt indication bit (fifoerri) reports a fifo overrun/underrun error event. fifo overrun/underrun errors occur when fifo logic detects fifo read and write pointers in close proximity to each other. fifoerri is set to logic 1 on a fifo overrun/underrun error. fifoerri is set to logic 0 when the t8te interrupt status register is read. this bit does not cause a hardware interrupt on intb, unless the fifoerre bit is set high.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 416 register 0862h: t8te aps1 telecombus mode #1 register 086ah: t8te aps2 telecombus mode #1 register 0872h: t8te aps3 telecombus mode #1 register 087ah: t8te aps4 telecombus mode #1 bit type function default bit 15 r/w reserved 0 bit 14 r/w reserved 0 bit 13 r/w reserved 0 bit 12 r/w reserved 0 bit 11 r/w reserved 0 bit 10 r/w reserved 0 bit 9 r/w reserved 0 bit 8 r/w reserved 0 bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w reserved 0 this register is reserved and should be forced to all zeros.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 417 register 0863h: t8te aps1 telecombus mode #2 register 086bh: t8te aps2 telecombus mode #2 register 0873h: t8te aps3 telecombus mode #2 register 087bh: t8te aps4 telecombus mode #2 bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w reserved 0 this register is reserved and should be forced to all zeros.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 418 register 0864h: t8te aps1 test pattern register 086ch: t8te aps2 test pattern register 0874h: t8te aps3 test pattern register 087ch: t8te aps4 test pattern bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 r/w tp[9] 1 bit 8 r/w tp[8] 0 bit 7 r/w tp[7] 1 bit 6 r/w tp[6] 0 bit 5 r/w tp[5] 1 bit 4 r/w tp[4] 0 bit 3 r/w tp[3] 1 bit 2 r/w tp[2] 0 bit 1 r/w tp[1] 1 bit 0 r/w tp[0] 0 tp[9:0]: the test pattern registers (tp[9:0]) contains the test pattern that is used to insert into the outgoing data stream for jitter test purpose. when the tpins bit is set high, the test pattern stored in tp[9:0] is used to replace all the overhead and payload bytes of the output data stream.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 419 register 0865h: t8te aps1 analog control register 086dh: t8te aps2 analog control register 0875h: t8te aps3 analog control register 087dh: t8te aps4 analog control bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 reserved 0 bit 9 reserved 0 bit 8 r/w txlv_enb 1 bit 7 r/w piso_enb 1 bit 6 r/w atin[3] 0 bit 5 r/w atin[2] 0 bit 4 r/w atin[1] 0 bit 3 r/w atin[0] 0 bit 2 r/w txlv_atmsb 1 bit 1 r/w piso_atmsb 1 bit 0 r/w arstb 1 arstb: the analog reset bit (arstb) controls the txlv and piso operation. when arstb is set low, the txlv and piso are reset. this bit must be set to logic 1 for normal operation. piso_atmsb: the piso analog test mode select bit (piso_atmsb) controls the piso test operation. piso_atmsb drives the output piso_atmsb pin low to enable test mode in the piso. this bit must be set to logic 1 for normal operation. txlv_atmsb: the txlv analog test mode select bit (txlv_atmsb) controls the txlv test operation. txlv_atmsb drives the output txlv_atmsb pin low to enable test mode in the txlv block. this bit must be set to logic 1 for normal operation.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 420 atin[3:0]: the analog test control inputs (atin[3:0]) control the piso and txlv test circuitry. these bits are not used for normal operation. piso_enb: the piso enable bit (piso_enb) controls the piso operation. when set to logic 1, piso_enb disables the piso. when set to logic 0, piso_enb enables the piso. txlv_enb: the txlv enable bit (txlv_enb) controls the txlv operation. when set to logic 1, txlv_enb disables the txlv. when set to logic 0, txlv_enb enables the txlv. reserved: the reserved bits should be set to logic 0 for proper operation.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 421 register 0866h: t8te aps1 dtb bus register 086eh: t8te aps2 dtb bus register 0876h: t8te aps3 dtb bus register 087eh: t8te aps4 dtb bus bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused bit 7 r/w dtbo[0] 0 bit 6 r/w dtbo[0] 0 bit 5 r/w dtbo[0] 0 bit 4 r/w dtbo[0] 0 bit 3 r dtbi[3] 0 bit 2 r dtbi[2] 0 bit 1 r dtbi[1] 0 bit 0 r dtbi[0] 0 dtbo[3:0] the analog wrapper digital test bus output bits (dtb_out[3:0]) are used to drive values on the digital test bus (dtb[3:0]). these bits are not used in normal operation. dtbi[3:0] the analog wrapper digital test bus input bits (dtb_in[3:0]) are used to read values from the digital test bus (dtb[3:0]). thee bits are not used in normal operation.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 422 register 0880h-0883h : rfclk dll reserved
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 423 register 0884h-0887h : tfclk dll reserved
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 424 register 0888h : cstr control bit type function default bit 15 r/w reserved 0 bit 14 r/w reserved 0 bit 13 r/w reserved 0 bit 12 r/w reserved 0 bit 11 unused x bit 10 r/w reserved 1 bit 9 r/w reserved 0 bit 8 r/w reserved 0 bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 1 bit 3 r/w reserved 0 bit 2 r/w reserved x bit 1 r/w reserved x bit 0 r/w reserved 1 except for the csu_enb register bit, the other register bits are used for manufacturing test purposes only. they are not required for normal operations. reserved:
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 425 register 0889h : cstr interrupt enable and csu lock status bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 1 unused x bit 1 r csu_lockv x bit 0 r/w csu_locke 0 csu_locke: the csu lock interrupt enable bit (csu_locke) enables the assertion of a hardware interrupt on intb when the csu lock status changes. when csu_locke is logic 1, the hardware interrupt is enabled. when csu_locke is logic 0, the hardware interrupt is disabled. csu_lockv: the csu lock status (csu_lockv) indicates the current state of the csu. when csu_lockv is logic 1, the csu has locked on to the sysclk reference and is operating normally. when csu_lockv is logic 0, the csu has not locked onto the sysclk reference and is not in normal operating mode.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 426 register 088ah : cstr csu lock interrupt indication bit type function default bit 15 unused x bit 14 unused x bit 13 unused x bit 12 unused x bit 11 unused x bit 10 unused x bit 9 unused x bit 8 unused x bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 1 unused x bit 1 unused x bit 0 r csu_locki x csu_locki: the csu lock interrupt indication bit (csu_locki) reports changes in the csu lock status. csu_locki is logic 1 when the csu transitions to or out of lock state. csu_locki is cleared when this register is read.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 427 register 088bh : cstr csu lock interrupt indication
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 428 register 0890h-0897 : s/uni-2488 rx stsi reserved
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 429 register 0898h-089f : s/uni-2488 tx stsi reserved
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 430 12 operation 12.1.1 lvds overview the lvds aps port implements the 777.6 mb/s lvds links. a reference clock of 77.76mhz is required (which is generated from the s/uni-2488 csu). four 777.6 mb/s lvds form a high- speed serial telecombus interface for passing an sts-48 aggregate data stream. a generic lvds link according to ieee 1596.3-1996 is illustrated below. the transmitter drives a differential signal through a pair of 50 ? characteristic interconnects, such as board traces, backplane traces, or short lengths of cable. the receiver presents a 100 ? differential termination impedance to terminate the lines. included in the standard is sufficient common-mode range for the receiver to accommodate as much as 925mv of common-mode ground difference. figure 17: generic lvds link block diagram ? zo=50 zo=50 ? 100? v op v on v ip v in transmitter interconnect receiver complete serdes transceiver functionality is provided. ten-bit parallel data is sampled by the line rate divided-by-10 clock (77.76mhz sysclk) and then serialized at the line rate on the lvds output pins by a 777.6mhz clock synthesized from a divided version of refclk. serial line rate lvds data is sampled and de-serialized to 10-bit parallel data. parallel output transfers are synchronized to a gated line rate divided-by-10 clock. the 10-bit data is passed to an 8b/10b decoding block. the gating duty cycle is adjusted such that the throughput of the parallel interface equals the receive input data rate (line rate +/- 100ppm). it is expected that the clock source of the transmitter is the same as the clock source of the receiver to ensure the data throughput at both ends of the link are identical. data must contain sufficient transition density to allow reliable operation of the data recovery units. 8b/10b block coding and decoding is provided by the t8te and r8td blocks.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 431 at the system level, reliable operation will be obtained if proper signal integrity is maintained through the signal path and the receiver requirements are respected. namely, a worst case eye opening of 0.7ui and 100mv differential amplitude is needed. these conditions should be achievable with a system architecture consisting of board traces, two sets of backplane connectors and up to 1m of backplane interconnects. this assumes proper design of 100 ? differential lines and minimization of discontinuities in the signal path. due to power constraints, the output differential amplitude is approximately 350mv. the lvds system is comprised of the lvds receiver (rxlv), data recovery unit (dru), receive 8b/10b telecombus decoder (r8td), transmit 8b/10b telecombus encoder (t8te), aps parallel to serial converter (apiso), lvds transmitter (txlv) and transmitter lvds reference (txlvref), and clock synthesis unit (csu) blocks. 12.1.2 lvds receiver (rxlv) the rxlv abc is a 777.6 mb/s low voltage differential signaling (lvds) receiver according to the ieee 1596.3-1996 lvds specification. the rxlv abc is the receiver accepts up to 777.6 mb/s lvds signals from the transmitter, amplifies them, converts them to digital signals and passes them to a data recovery unit (dru). as per to the ieee 1596.3-1996 specification, the rxlv has a differential input sensitivity better than 100mv, and includes at least 25mv of hysteresis. 12.1.3 data recovery unit (dru) the dru is a fully integrated data recovery and serial to parallel converter which is used for 777.6 mb/s nrz data. an 8b/10b block code is used to guarantee transition density for optimal performance. the dru recovers data and outputs a 10-bit word synchronized with a line rate divided by 10 gated clock to allow frequency deviations between the data source and the local oscillator. the dru accumulates 10 data bits and outputs them on the next clock edge. the dru provides moderate high frequency jitter tolerance suitable for inter-chip serial link applications. it can support frequency deviations up to 100ppm. 12.1.4 receive 8b/10b telecombus decoder (r8td) the r8td works in conjunction with the upstream dru that packs consecutive bits from an incoming 8b/10b serial link into a 10-bit wide stream with arbitrary alignment to the 8b/10b character boundaries. the r8td character alignment block uses the k28.5 control character (comma control / transport frame alignment) to determine 8b/10b character alignment in the incoming stream. when the r8td character alignment state machine is in the out-of-character-alignment state, it searches for the k28.5 character in all positions of the incoming stream. upon detecting the k28.5 character, the r8td will align its internal character boundary, the character alignment state machine will transition to the in-character-alignment state and cease searching for subsequent k28.5
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 432 characters. the character alignment block also monitors for line-code violations (lcv) which are accumulated in an internal register. if 5 or more lcvs are detected within a window of 15 characters, the r8td will enter the out-of-character-alignment state and begin searching for the k28.5 character afresh. when operating in fifo mode, aligned characters are written into a 24-character fifo that isolates the incoming timing domain from the outgoing timing domain and provides a means of synchronizing multiple r8tds outputs. otherwise, the fifo is bypassed. in order to allow synchronization with other r8tds that may have slightly different frame alignment and to allow for frame re-alignment, the r8td frame alignment block monitors the character aligned data stream for the k28.5. an internal frame counter is maintained based on this character. if the k28.5 is found out of place three times then the frame alignment moves to the out-of-frame-alignment state. when in the out-of-frame-alignment state the first k28.5 will be written to the 0 position of the fifo. the read pointer is then set by the oj0fp signal to synchronize the output of the k28.5 characters which ensures that signals leaving the multiple r8tds will have the same alignment. the r8td decodes 8b/10b control characters associated with specific sonet/sdh byte positions in an extended telecombus stream. in order to identify more sonet/sdh bytes than the 12 control characters available in the standard set, those control characters with balanced line codes for both positive and negative running disparity (k28.0, k28.4, k38.7, k23.7, k27.7, k29.7 and k30.7) are treated specially, where the positive and negative disparity codes are each associated with a different sonet/sdh byte. the reception of these line-codes will not be considered lcvs due to a mismatch with the running disparity. the r8td provides a diagnostic loopback port where the outgoing stream from an associated transmit 8b/10b encoder block (t8te) can be processed in place of the incoming stream. 12.1.5 transmit 8b/10b telecombus encoder (t8te) the t8te encodes a telecombus data stream and encodes it into an extended 8b/10b format for transmission on the serial lvds links. the t8te encodes telecombus control signals such as transport frame and payload boundaries, pointer justification events and alarm conditions into three levels of extended set of 8b/10b characters as well as performing the ieee mode conversion on data. in order to identify more telecombus bytes and events than the 12 control characters available in the standard set, those control characters with balanced line codes for both positive and negative running disparity (k28.0, k28.4, k28.5, k28.6, k28.7, k23.7, k27.7, k29.7 and k30.7) are treated specially. the positive and negative disparity codes are each associated of a different sonet/sdh byte or event. the t8te can be configured to operate in the loopback mode which allows a line loopback from the associated r8td block. the t8te can be configured to use a fifo to bridge between the incoming data stream and the outgoing data stream clock domains.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 433 12.1.6 aps parallel to serial converter (piso) the apiso is a parallel-to-serial converter designed for high-speed transmit operation, supporting up to 777.6 mb/s. 12.1.7 lvds transmitter (txlv) the txlv is a 777.6 mb/s low voltage differential signaling (lvds) transmitter according to the ieee 1596.3-1996 lvds specification. the txlv accepts 777.6 mbit/s differential data from the apsio circuit and transmits the data off-chip as a low voltage differential signal. the txlv uses the reference current and voltage from the txlvref to control the output differential voltage amplitude and the output common-mode voltage. 12.2 sonet/sdh frame mappings and overhead byte usage 12.2.1 atm mapping the s/uni-2488 processes the atm cell mapping for sts-48c (stm-16c) as shown below in figure 18. the s/uni-2488 processes the transport and path overhead required to support atm unis and nnis. in addition, the s/uni-2488 provides support for the aps bytes, the data communication channels and provides full control and observability of the transport and path overhead bytes through register access. in figure 18, the sts-48c (stm-16c) mapping is shown. in this mapping, fifteen stuff columns are included in the spe. no other options are provided. figure 18 atm mapping section overhea d line overhea d pointer 4320 bytes 4176 bytes j1 b3 c2 g1 atm cell 9 bytes f2 h4 z3 z4 z5 transport overhea d f i x e d s t u f f f i x e d s t u f f atm cell atm cell atm cell 12.2.2 packet over sonet mapping the s/uni-2488 processes the packet over sonet mapping for sts-48c (stm-16c) as shown below in figure 19. the s/uni-2488 processes the transport and path overhead required to support packet over sonet applications. in addition, the s/uni-2488 provides support for the
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 434 aps bytes, the data communication channels and provides full control and observability of the transport and path overhead bytes through register access. figure 19, the sts-48c (stm-16c) mapping is shown. in this mapping, the entire spe is used for pos frames. figure 19 packet over sonet mapping section overhead line overhead pointer 4320 bytes 4176 bytes j1 b3 c2 g1 pos frame pos frame pos frame 9 bytes f2 h4 z3 z4 z5 transport overhead pos frame f i x e d s t u f f f i x e d s t u f f 12.2.3 transport and path overhead bytes transport overhead bytes a1, a2: the frame alignment bytes (a1, a2) locate the sonet frame in the sts-48c (stm-16c) serial stream. j0 the j0 byte is currently defined as the sts-48c (stm-16c) section trace byte for sonet/sdh. j0 byte is not scrambled by the frame synchronous scrambler. z0: the z0 bytes are currently defined as the sts-48c (stm-16c) section growth bytes for sonet/sdh. z0 bytes are not scrambled by the frame synchronous scrambler. b1: the section bit interleaved parity byte provides a section error monitoring function. in the transmit direction, the s/uni-2488 calculates the b1 byte over all bits of the previous frame after scrambling. the calculated code is then placed in the current frame before scrambling. in the receive direction, the s/uni-2488 calculates the b1 code over the current frame and compares this calculation with the b1 byte received in the following frame. b1 errors are accumulated in an error event counter. d1 - d3: the section data communications channel provides a 192 kbit/s data communications channel for network element to network element communications.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 435 h1, h2: the pointer value bytes locate the path overhead column in the sonet/sdh frame. in the transmit direction, the s/uni-622-pos inserts a fixed pointer value, with a normal new data flag indication in the first h1-h2 pair. the concatenation indication is inserted in the remaining h1-h2 pairs (sts-48c (stm-16c)). pointer movements can be induced using the thpp registers. in the receive direction, the pointer is interpreted to locate the spe. the loss of pointer state is entered when a valid pointer cannot be found. path ais is detected when h1, h2 contain an all ones pattern. h3: the pointer action bytes contain synchronous payload envelope data when a negative stuff event occurs. the all zeros pattern is inserted in the transmit direction. this byte is ignored in the receive direction unless a negative stuff event is detected. b2: the line bit interleaved parity bytes provide a line error monitoring function. in the transmit direction, the s/uni-2488 calculates the b2 values. the calculated code is then placed in the next frame. in the receive direction, the s/uni-2488 calculates the b2 code over the current frame and compares this calculation with the b2 code receive in the following frame. receive b2 errors are accumulated in an error event counter. k1, k2: the k1 and k2 bytes provide the automatic protection switching channel. the k2 byte is also used to identify line layer maintenance signals. line rdi is indicated when bits 6, 7, and 8 of the k2 byte are set to the pattern '110'. line ais is indicated when bits 6, 7, and 8 of the k2 byte are set to the pattern '111'. in the transmit direction, the s/uni-2488 provides register control for the k1 and k2 bytes. in the receive direction, the s/uni-2488 provides register access to the filtered aps channel. protection switch byte failure alarm detection is provided. the k2 byte is examined to determine the presence of the line ais, or the line rdi maintenance signals d4 - d12: the line data communications channel provides a 576 kbit/s data communications channel for network element to network element communications. s1: the s1 byte provides the synchronization status byte. bits 5 through 8 of the synchronization status byte identifies the synchronization source of sts-48c (stm-16c) signal. bits 1 through 4 are currently undefined.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 436 in the transmit direction, the s/uni-2488 provides register control for the synchronization status byte. in the receive direction, the s/uni-2488 provides register access to the synchronization status byte. z1: the z1 bytes are located in the second and third sts-1?s locations of an sts- 48c (stm-16c) and are allocated for future growth. m1: the m1 byte is located in the third sts-1 location of a sts-48c (stm-16c) and provides a line far end block error function for remote performance monitoring. z2: the z2 bytes are located in the first and second sts-1?s locations of a sts- 12c (stm-4c) and are allocated for future growth. in the transmit direction, z2 byte is internally generated. the number of b2 errors detected in the previous interval is inserted. in the receive direction, a legal z2 byte value is added to the line febe event counter. path overhead bytes j1: the path trace byte is used to repetitively transmit a 64-byte clli message (for sonet networks), or a 16-byte e.164 address (for sdh networks). when not used, this byte should be set to transmit continuous null characters. null is defined as the ascii code, 0x00. in the transmit direction, characters can be inserted using the tttp path trace register. the register is the default selection and resets to 0x00 to enable the transmission of null characters from a reset state. in the receive direction, the path trace message is optionally extracted into the 16 or 64 byte path trace message buffer. b3: the path bit interleaved parity byte provides a path error monitoring function. in the transmit direction, the s/uni-2488 calculates the b3 bytes. the calculated code is then placed in the next frame. in the receive direction, the s/uni-2488 calculates the b3 code and compares this calculation with the b3 byte received in the next frame. b3 errors are accumulated in an error event counter. c2: the path signal label indicator identifies the equipped payload type. for atm payloads, the identification code is 0x13. for packet over sonet (including x 43 +1 payload scrambling), the identification code is 0x16.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 437 g1: the path status byte provides a path rdi function, and a path remote defect indication function. three bits are allocated for remote defect indications: bit 5 (the path rdi bit), bit 6 (the auxiliary path rdi bit) and bit 7 (enhanced rdi bit). taken together these bits provide a eight state path rdi code that can be used to categorize path defect indications. in the transmit direction, the s/uni-2488 provides register bits to control the path rdi (bit 5) and auxiliary path rdi (bit 6) states. for path rdi, the number of b3 errors detected in the previous interval is inserted either automatically or using a register. this path rdi code has 9 legal values, namely 0 to 8 errors. in the receive direction, a legal path rdi value is accumulated in the path rdi event counter. in addition, the path rdi and auxiliary path rdi signal states are available in internal registers. h4: the multi-frame indicator byte is a payload specific byte, and is not used for atm payloads. this byte is forced to 0x00 in the transmit direction, and is ignored in the receive direction. z3 - z5: the path growth bytes provide three unused bytes for future use. in the transmit direction, the growth bytes may be inserted from the three thpp path growth byte registers. 12.2.4 atm cell data structure atm cells may be passed to/from the s/uni-2488 using a 52 byte cell structure on a 32-bit utopia level 3 compliant interface. figure 20 shows the default atm cell format for the s/uni-2488 at the utopia level 3 interface. it is the 13x32-bit word structure with no hcs or udf bytes.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 438 bit 31 of each word is the most significant bit (which corresponds to the first bit transmitted or received). the start of cell indication input and output (tsoc and rsoc) are coincident with word 1 (containing the first four header octets). figure 20: a 52 byte atm data structure bit 31 bit 16 bit 15 bit 0 word 1h1h2h3h4 word 2 payload 1 payload 2 payload 3 payload 4 word 3 payload 5 payload 6 payload 7 payload 8 . . . . . . . . . . . . . . . word 12 payload 41 payload 42 payload 43 payload 44 word 13 payload 45 payload 46 payload 47 payload 48 12.3 pos/hdlc data structure packets may be passed to/from the s/uni-2488 using a 32-bit pos-phy level 3 compliant interface. the 32-bit pos-phy level 3 data structure is shown in figure 21. the packet length of 63 bytes is chosen arbitrarily for illustrative purposes only. other lengths are acceptable. octets are written in the same order they are to be transmitted or they were received on the sonet line. all words are composed of four octets, except the last word of a packet which can have one, two, three, or four octets. if the transmit packet processor (tcfp) is configured to not insert the fcs field, then these bytes should be included with the packet passed through the pos-phy l3 interface. similarly, if the receive packet processor (rcfp) is configured to not strip the fcs field, then these bytes will be included at the end of the packet. figure 21: a 63 byte packet data structure bit 31 bit 16 bit 15 bit 0 word 1 byte 1/sop byte 2 byte 3 byte 4 word 2 byte 5 byte 6 byte 7 byte 8 word 3 byte 9 byte 10 byte 11 byte 12 . . . . . . . . . . . . . . . word 15 byte 57 byte 58 byte 59 byte 60 word 16 byte 61 byte 62 byte 63/eop unused both the start of the packet and the end of the packet must be identified by the tsop/rsop and teop/reop signals. when the first section of a packet is transferred over the interface, the
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 439 tsop/rsop signals will be high for byte 1 of the packet only. the tmod[1:0] pins will indicate how many bytes of the final word are valid. bits 31 to 24 form the first transmitted byte and bit 31 can be configured to be the bit which is transmitted first. this is the desired set-up for byte-synchronous pos. bit 24 can also be configured to be the first transmitted bit of this byte. this is the desired set-up for bit-synchronous hdlc. 12.3.1 limitation when using externally generated fcs in sts-48c mode when the s/uni-2488 is set up in sts-48c pos mode and fcs bytes are passed through the transmit pos-phy l3 interface, the overall throughput is reduced. the maximum bandwidth throughput will be reduced by a maximum of 2 bytes per packet. the overall effect will depend on the length of the packets + fcs bytes being transferred through the pos-phy l3 interface. if the packet + fcs length is evenly divisible by 4 bytes, no bandwidth is lost for that packet. 12.3.2 limitations from small packets the s/uni-2488 cannot process packets which are smaller than 4 bytes (including fcs). packets of size 3 bytes or less are discarded by the rcfp packet processor and marked as minimum length violations. 12.4 setting atm mode of operation tbd 12.5 setting packet over sonet/sdh mode of operation tbd 12.6 bit error rate monitor tbd 12.7 clocking operations tbd 12.8 loopback operation tbd
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 440 12.9 board design recommendations tbd 12.10 power supplies tbd 12.11 interfacing to ecl or pecl devices tbd
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 441 13 functional timing 13.1 serial line interface tbd 13.2 atm utopia level 3 system interface the receive utopia level 3 system interface timing diagrams figure 22 and figure 23 illustrate the operation of the system side receive interface. the single phy case shown in figure 22 illustrates the behaviour of the rca signal. at the start cycle 3, renb is sampled low which initiates a cell transfer from the s/uni-2488. the transfer begins at cycle 4. the response to renb always occurs on the rising rfclk edge following the rfclk edge which samples renb. also note that renb must remain asserted during a cell transfer as specified by the utopia l3 standard. in figure 22, this occurs on the rising edge of rfclk at the start of cycle 9. rca is deasserted in cycle 11 coincident with the rsoc assertion indicating that the cell transfer which has just started contains the last cell in the fifo at this time. rca may be asserted at any time due to the insertion of a complete cell into the fifo. back-to-back cells can be handled by holding renb asserted at logic 0 during cycle 8. in this case, cycle 10 for rsoc, rdat[31:0], and rprty will be eliminated and the following cycles will be advanced. figure 22 single-phy utopia level 3 receive functional timing 1 2 3 4 5 6 7 8 9 10 11 12 h1 p1 p10 p11 p12 h1 p1 rfclk rca renb rsoc rdat[31:0] rprty
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 442 the transmit utopia level 3 system interface timing diagram (figure 23) illustrates the operation of the system side transmit ul3 interface. the single phy case shown figure 23 illustrates the behaviour of the tca signal. at the start of cycle 4, there is only enough fifo buffer space for the cell being transferred so tca is deasserted. the deassertion occurs on the tfclk edge after tsoc of the cell (cell#1) being written to the fifo is sampled. this cell will take the last remaining cell buffer space in the fifo. this tca behaviour is consistent with the utopia l3 specification which states that tca is invalid on the tfclk edge that initiates the transition of tsoc to logic 1. on cycle 5, a cell has been read out of the fifo to the s/uni-2488 core so it now has room to accomodate the cell currently being transferred (cell#1) plus one additional cell (cell#2). at the start of cycle 8, the transfer of cell#1 is completed. tca remains high because there is still buffer space for one more cell. at the start of cycle 10, transfer of cell#2 starts. tca is deasserted at cycle 11 because besides the space for holding cell#2, there is no fifo space for any more cells. note that the single-phy mode is handled exactly like the multi-phy mode except that the phy address is held at the value 0. however, tenb must be set to logic 1 between cell transfers as shown in figure 23. back-to-back cell transfers is not allowed. tsoc must be high during the first byte of the atm cell structure and must be present for the start of each cell. thus, tsoc will mark the h1 byte. if tsoc is asserted at the wrong time (not at proper cell boundaries), a corrupted (but complete) cell will be transmitted from the s/uni- 2488. this corrupted cell will contain the bytes from the runt cell transferred through the ul3 interface plus some random bytes to fill the remainder of the atm cell. figure 23 single-phy utopia level 3 transmit functional timing 1 2 3 4 5 6 7 8 9 10 11 12 h1 p1 p2 p3 p12 h1 p1 p2 p3 tfclk tca tenb tsoc tdat[31:0] tprty
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 443 13.3 packet over sonet/sdh (pos) level 3 system interface the receive pos level 3 system interface timing diagram (figure 24) illustrates the operation of the system side receive interface. the suni-2488 performs the polling operation internally, selects the phy for which data is to be transferred, and pushes data to the downstream reader. when data is available, the rval signal is asserted. rsx is also asserted in cycle 2 to indicate that the phy address for which data is being transferred is present on rdat[31:0]. at cycle 3, rsop is asserted to indicate that the rdat[31:24] contains the first byte of a packet. renb is deasserted in cycle 4 because the downstream device wants to pause the data transfer. data transfer continues until cycle 10 when rval is deasserted. at cycle 12 and 13, the last two transfers for the packet are performed. in cycle 13, reop signals the last byte of the packet is contained in rdat[31:0] and the value of rmod[1:0] indicates which bytes in rdat[31:0] contain valid data. rerr is asserted along with reop if errors were detected in this packet (aborted, length violation, fifo overrun, fcs errors) so the downstream device may discard the packet. in cycle 14, a new transfer is initiated by reasserting rsx and a new phy address on rdat[31:0]. the burst length of any transfer can be limited by setting the rxphy?s burst_size[7:0] register bits. the polling algorithm used for selecting the order in which data from different phys are transferred is completely user programmable using the calendar_length[6:0], calendar_addr[6:0] and calendar_data[5:0] register bits of the rxphy. the fifo threshold at which data transfer begins is set by the rxsdq?s dt[7:0] register bits. atm cells can be transferred through the pl3 interface as fixed length packets. the dt[7:0] value should be set so that only complete atm cells are transferred.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 444 figure 24 single phy pos-phy level 3 receive functional timing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 000 b1- b b5- b b9-b12 b41 b4 5 b5 2 b5 6 000 b 2 rfclk renb rsx rsop reop rerr rmod[1:0] rdat[31:0] rprty r val the transmit pos level 3 system interface timing (figure 25) illustrates the operation of the system side transmit fifo interface. tenb, tsx, and tdat[31:0] (which contains the in-band phy address since tsx = 1) are asserted in cycle 1 to start the transfer. because the s/uni- 2488 is a single-phy device, the in-band address must always be set to 0x0000. dtpa responds in cycle 3 to show that there is room in the fifo (the fifo fill threshold is user programmable) for phy address 0. the packet data is transferred on tdat[31:0] starting at the rising tfclk edge at the start of cycle 3. tsop is also asserted at this cycle to indicate the data on tdat[31:24] contains the start-of-packet byte. tenb is deasserted in cycle 3 by the upstream device to pause the transfer. data transfer continues in cycle 4. in cycle 6, dtpa is deasserted indicating that the fifo for phy address 0 has fallen below the data available threshold (txsdq?s bt[7:0] register bits). in the example shown here, bt[7:0] is set to the value 1 so that dtpa is deasserted when there is less than 16 bytes of buffer space left in the fifo. the txsdq fifo status takes 1 clock cycle to propagate to the interface so after the upstream device samples dtpa at the rising tfclk edge at the start of cycle 7, it can only write one more cycle of tdat[31:0] before it must stop to avoid overrunning the fifo. tenb is deasserted before cycle 9 to prevent the overrun. the txsdq hysteresis value (ght[3:0] should be used to prevent the dtpa signal from pulsating on and off while the fifo is at the ba[7:0] threshold.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 445 because dtpa is asserted again on cycle 8, transfers can be conducted again. tenb is asserted again before cycle 11 to continue the transfer. in cycle 11, teop is asserted to indicate that tdat[31:0] contains one byte which is the end of the packet. tmod[1:0] is valid at the same time to indicate which bytes in tdat[31:0] contain valid data and thus the last byte of the packet can be inferred. terr is also valid during this cycle to indicate whether or not this packet should be aborted because of an upstream error. if terr is logic 1, the packet will be aborted by the s/uni-2488?s packet processor. in cycle 12, tenb is deasserted and tsx is asserted to select a different phy to transfer data to. tsop must be high during transfers which contain the first byte of a packet. teop must be high during transfers which contain the last byte of a packet. it is legal to assert tsop and teop at the same time. this case occurs when tdat[31:0] contain both the sop and eop. when tsop is asserted and the previous transfer was not marked with teop, the system interface realigns itself to the new timing, and both the previous packet and the current packet may be corrupted and aborted. figure 25 single phy pos-phy level 3 transmit functional timing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 000 b1- b b5- b b41 b4 5 b4 9 b5 3 b5 7 000 b1- tfclk tenb tsx tsop teop tmod[1:0] terr tdat[31:0] tprty dtpa
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 446 13.4 section and line data communication channels tbd 13.5 s/uni-2488 conceptual regions the s/uni-2488 can conceptually be split into 3 regions: line side timeslots, system side timeslots, and system side channels. each region has its data streams segregated differently and has a transmit half and a receive half.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 447 14 test features description
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 448 15 functional timing
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 449 16 absolute maximum ratings maximum rating are the worst case limits that the device can withstand without sustaining permanent damage. they are not indicative of normal mode operation conditions. table 17: absolute maximum ratings case temperature under bias -40c to +85c storage temperature -40c to +125c supply voltage tbd voltage on any digital pin -0.3v to v vdd +0.3v static discharge voltage 1000 v latch-up current 100 ma dc input current 20 ma lead temperature +230c absolute maximum junction temperature +150c
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 450 17 d.c. characteristics t c = -40c to +85c, v dd = vdd typical 10% (typical conditions: t c = 25c, v vdddc = 1.8v, v vddac = 3.3v, v av d h = 3.3v +/- 5% only, v avdl = 1.8v +/- 5% only, v qavd = 3.3v +/- 5% only) table 18: d.c characteristics symbol parameter min typ max units conditions v vddi power supply 1.62 1.8 1.98 volts v vddo power supply 2.97 3.3 3.63 volts v avdd power supply 2.97 3.3 3.63 volts v avddq power supply 2.97 3.3 3.63 volts v il input low voltage 0 tbd 0.8 volts guaranteed input low voltage. v ih input high voltage 2.0 tbd volts guaranteed input high voltage. v ol output or bi- directional low voltage tbd 0.4 volts guaranteed output low voltage at vdd=2.97v and i ol =maximum rated for pad. v oh output or bi- directional high voltage 2.4 tbd volts guaranteed output high voltage at vdd=2.97v and i oh =maximum rated current for pad. v t+ reset input high voltage 2.0 volts applies to rstb and trstb only. v t- reset input low voltage 0.8 volts applies to rstb and trstb only. v th reset input hysteresis voltage tbd volts applies to rstb and trstb only. i ilpu input low current tbd tbd tbd a v il = gnd. notes 1 and 3.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 451 i ihpu input high current tbd tbd tbd a v ih = v dd . notes 1 and 3. i il input low current tbd tbd tbd a v il = gnd. notes 2 and 3. i ih input high current -10 0 +10 a v ih = v dd . notes 2 and 3. v icm lvds input common- mode range 02.4v |v idm | lvds input differential sensitivity 100 mv r in lvds differential input impedance 85 100 115 ? v loh lvds output voltage high 1375 1475 mv r load =100 ? 1% v lol lvds output voltage low 925 1025 mv r load =100 ? 1% v odm lvds output differential voltage 300 350 400 mv r load =100 ? 1% v ocm lvds output common-mode voltage 1125 1200 1275 mv r load =100 ? 1% r o lvds output impedance, differential 85 110 115 ? | ? v odm | change in |v odm | between ?0? and ?1? 25 mv r load =100 ? 1% ? v ocm change in v ocm between ?0? and ?1? 25 mv r load =100 ? 1% i sp , i sn lvds short-circuit output current 10 ma drivers shorted to ground i spn lvds short-circuit output current 10 ma drivers shorted together c in input capacitance 5 pf t a =25c, f = 1 mhz c out output capacitance 5pft a =25c, f = 1 mhz c io bi-directional capacitance 5pf t a =25c, f = 1 mhz
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 452 i ddop1 operating current tbd ma v dd = max, outputs unloaded i ddop2 operating current tbd ma v dd = max, outputs unloaded i ddop3 operating current tbd ma v dd = max, outputs unloaded i ddop4 operating current tbd ma v dd = max, outputs unloaded notes on d.c. characteristics: 1. input pin or bi-directional pin with internal pull-up resistor. 2. input pin or bi-directional pin without internal pull-up resistor 3. negative currents flow into the device (sinking), positive currents flow out of the device (sourcing).
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 453 18 microprocessor interface timing characteristics (t c = -40c to +85c, v dd = typical 10%) table 19: microprocessor interface read access (figure 26) symbol parameter min max units ts ar address to valid read set-up time 10 ns th ar address to valid read hold time 5 ns ts alr address to latch set-up time 10 ns th alr address to latch hold time 10 ns tv l valid latch pulse width 5 ns ts lr latch to read set-up 0 ns th lr latch to read hold 5 ns tp rd valid read to valid data propagation delay 70 ns tz rd valid read negated to output tri-state 20 ns tz inth valid read negated to intb high 50 ns
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 454 figure 26: intel microprocessor interface read timing vali d tzrd tprd tzinth thlr tslr thalr tvl tsalr tvl thar tsar a[13:0] ale (csb+rdb) intb d[15:0] notes on microprocessor interface read timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum output propagation delays are measured with a 100 pf load on the microprocessor interface data bus, (d[15:0]). 3. a valid read cycle is defined as a logical or of the csb and the rdb signals. 4. in non-multiplexed address/data bus architectures, ale should be held high so parameters ts alr , th alr , tv l , ts lr , and th lr are not applicable. 5. parameter th ar is not applicable if address latching is used. 6. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 7. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 455 table 20: microprocessor interface write access (figure 27) symbol parameter min max units ts aw address to valid write set-up time 10 ns ts dw data to valid write set-up time 20 ns ts alw address to latch set-up time 10 ns th alw address to latch hold time 10 ns tv l valid latch pulse width 5 ns ts lw latch to write set-up 0 ns th lw latch to write hold 5 ns th dw data to valid write hold time 5 ns th aw address to valid write hold time 5 ns tv wr valid write pulse width 40 ns figure 27: intel microprocessor interface write timing vali d thlw thdw tsdw tvwr tvwr tslw thalw tvl tsalw tvl thaw tsaw a[13:0] ale (csb+wrb) d[15:0]
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 456 notes on microprocessor interface write timing: 1 a valid write cycle is defined as a logical or of the csb and the wrb signals. 2 in non-multiplexed address/data bus architectures, ale should be held high so parameters ts alw , th alw , tv l , ts lw , and th lw are not applicable. 3 parameter th aw is not applicable if address latching is used. 4 when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 5 when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 457 19 a.c. timing characteristics table 21: receive system interface timing (figure 28) symbol description min max units f rfclk rfclk frequency 60 104 mhz thi rfclk rfclk hi pulse width 3.85 ns tlo rfclk rfclk lo pulse width 3.85 ns ts renb renb set-up time to rfclk 2 ns th renb renb hold time to rfclk 0.5 ns tp rval rfclk high to rca/rval valid 1 5 ns tp rsop rfclk high to rsoc/rsop valid 1 5 ns tp reop rfclk high to reop valid 1 5 ns tp rprty rfclk high to rprty valid 1 5 ns tp rerr rfclk high to rerr valid 1 5 ns tp rsx rfclk high to rsx valid 1 5 ns tp rdat rfclk high to rdat[31:0] valid 1 5 ns tp rmod rfclk high to rmod[1:0] valid 1 5 ns
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 458 figure 28: receive system interface timing diagram tprmod tprdat tprsx tprerr tprprty tpreop tprsop tprval threnb tsrenb thirfclk thirfclk tlorfclk tlorfclk rfclk renb rca/rval r soc/rsop reop rprty rerr rsx rdat[31:0] rmod[1:0]
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 459 table 22: transmit system interface timing (figure 29) symbol description min max units f tfclk tfclk frequency 60 104 mhz thi tfclk tfclk hi pulse width 3.85 ns tlo tfclk tfclk lo pulse width 3.85 ns ts tenb tenb set-up time to tfclk 2 ns th tenb tenb hold time to tfclk 0.5 ns ts tsop tsoc/tsop set-up time to tfclk 2 ns th tsop tsoc/tsop hold time to tfclk 0.5 ns ts teop teop set-up time to tfclk 2 ns th teop teop hold time to tfclk 0.5 ns ts tprty tprty set-up time to tfclk 2 ns th tprty tprty hold time to tfclk 0.5 ns ts terr terr set-up time to tfclk 2 ns th terr terr hold time to tfclk 0.5 ns ts tdat tdat[31:0] set-up time to tfclk 2 ns th tdat tdat[31:0] hold time to tfclk 0.5 ns ts tmod tmod[1:0] set-up time to tfclk 2 ns th tmod tmod[1:0] hold time to tfclk 0.5 ns tp tpa tfclk high to tca/dtpa valid 1 5 ns
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 460 figure 29: transmit system interface timing thterr tsterr thtprty tstprty thteop tsteop thtsop tstsop thtenb tstenb thitfclk thitfclk tlotfclk tlotfclk tfclk tenb tsoc/tsop teop tprty terr tptpa thtmod tstmod thtdat tstdat tdat[31:0] tmod[1:0] tca/dtpa
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 461 19.1 aps port interface symbol description min typical max units f rlvds apsi+/-[4:1], apso+/-[4:1] bit rate 5f sysclk - 100ppm 5f sysclk 5f sysclk - 100ppm mbps t fall v odm fall time, 80%-20%, (r load =100 ? 1%) 200 300 400 ps t rise v odm rise time, 20%-80%, (r load =100 ? 1%) 200 300 400 ps t skew differential skew 50 ps table 23: jtag port interface (figure 30) symbol description min max units f tck tck frequency 4 mhz thi tck tck hi pulse width 100 ns thi tck tck lo pulse width 100 ns ts tms tms set-up time to tck 25 ns th tms tms hold time to tck 25 ns ts tdi tdi set-up time to tck 25 ns th tdi tdi hold time to tck 25 ns tp tdo tck low to tdo valid 2 25 ns tv trstb trstb pulse width 100 ns
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 462 figure 30: jtag port interface timing tlotck tlotck thitck thitck tvtrstb tvtrstb tptdo thtms tstms thtdi tstdi tck tdi tms tdo trstb notes on input timing: 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 2. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. notes on output timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum output propagation delays are measured with a 30 pf load on the outputs except when otherwise specified.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 463 20 ordering and thermal information table 24: ordering information part no. description PM5381-BI 416-pin ultra ball grid array (ubga) table 25: thermal information part no. case temperature theta ja theta jc PM5381-BI -40c to 85c x c/w x c/w
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 464 21 mechanical information d a1 ball corner a aaa (4x) a1 ball id ink mark b e top view c 0.30 0.10 c ab s s b 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 21 23 22 24 25 26 27 28 29 30 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak e1, n e s extent of encapsulation e s d1, m a1 ball corner bottom view bbb c a2 a1 a c seating plane side view notes: 1) all dimensions in millimeter. 2) dimension aaa denotes package body profile. 3) dimension bbb denotes parallel. 4) dimension ddd denotes coplanarity.
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-2000489 issue 1 saturn user network interface for 2488 mbit/s proprietary and confidentail to pmc-sierra inc., and for its customer?s internal use 465
preliminary pmc-sierra, inc. pm5381 s/uni-2488 datasheet pmc-991044 issue 1 saturn user network interface for 2488 mbit/s none of the information contained in this document constitutes an express or implied warranty by pmc-sierra, inc. as to the suf ficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchanta bility, performance, compatibility with other parts or systems, of any of the products of pmc-sierra, inc., or any portion thereof, referred to in t his document. pmc-sierra, inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the inform ation, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-inf ringement. in no event will pmc-sierra, inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not pmc-sierra, inc. has been advised of the possibility of such damage. ? 2000 pmc-sierra, inc. pmc-2000489 (p1) ref pmc-991408 (p1) issue date: march 2000 pmc-sierra, inc.. 105 - 8555 baxter place burnaby, bc canada v5a 4v7 604 415.6000

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